Dynamic Program Erase Targeting with Bit Error Rate

2. The system of claim 1, wherein the processing device is further to, before placing the system into operation, determine a baseline BER based on factory default trim values, wherein the processing device is further to set the BER control value as a percentage above the baseline BER.

4. The system of claim 3, wherein the processing device is to perform each loop after execution of between tens to hundreds of program/erase cycles of the memory cells.

5. The system of claim 1, wherein the BER is based on one of a single codeword or a mean or a median of multiple codewords.

6. The system of claim 1, wherein the program targeting rule comprises locking of a program verify (PV) target of a programming distribution corresponding to a highest PV target.

8. The system of claim 1, wherein the program erase targeting operation is to implement the program targeting rule to further balance logical page types such that the BER is approximately a same BER for different logical page types, and to equalize relative valley margins of a particular logical page type such that read window budgets (RWB) for valleys of the particular logical page type are approximately a same RWB.

12. The method of claim 11, wherein repeating the loop comprises performing each loop after execution of between tens to hundreds of program/erase cycles of the memory cells.

18. The non-transitory computer-readable storage medium of claim 17, wherein repeating the operations as a loop comprises performing each loop after execution of between tens to hundreds of program/erase cycles of the memory array.

19. The non-transitory computer-readable storage medium of claim 15, wherein a valley having a lowest valley margin of the plurality of valley margins is between the erase distribution and a programming distribution adjacent to the erase distribution, and wherein performing the program erase targeting operation comprises reducing the voltage level associated with the erase distribution to increase a margin of the valley between the erase distribution and the programming distribution adjacent to the erase distribution.