Analog-To-Digital Conversion Circuit and Receiver Including Same

2. The analog-to-digital conversion circuit of claim 1, wherein a first degree to which the phase of the clock signal is shifted in the first direction is the same as a second degree to which the phase of the clock signal is shifted in the second direction.

3. The analog-to-digital conversion circuit of claim 1, wherein a first degree to which the phase of the clock signal is shifted in the first direction is different than a second degree to which the phase of the clock signal is shifted in the second direction.

4. The analog-to-digital conversion circuit of claim 3, wherein the first degree is greater than the second degree.

5. The analog-to-digital conversion circuit of claim 1, wherein the timing calibration circuit is further configured to adjust at least one of a number of the first samples, a number of the second samples, and a number of the third samples during at least one of the sampling periods in response to a change in a mode of operation for the analog-to-digital conversion circuit.

6. The analog-to-digital conversion circuit of claim 1, wherein the timing calibration circuit is further configured to control the phase of the clock signal applied to the second ADC in response to a change in a mode of operation for the analog-to-digital conversion circuit.

9. The analog-to-digital conversion circuit of claim 8, wherein the timing calibration circuit is further configured to decrease the value of the delay control signal when the change in the absolute value decreases, and to increase the value of the delay control signal when the change in the absolute value increases, to provide the changed delay control signal.

10. The analog-to-digital conversion circuit of claim 1, wherein the timing calibration circuit is further configured to perform a timing calibration operation in relation to the first ADC, the second ADC and the third ADC during timing calibration of the second ADC.

12. The receiver of claim 11, wherein the another ADC is an ADC among the ADCs disposed immediately before the target ADC, or an ADC among the ADCs disposed immediately after the target ADC.

13. The receiver of claim 11, wherein the timing calibration circuit is further configured to determine a shift direction for the phase of the clock signal in response to the change in absolute value.

14. The receiver of claim 13, wherein the timing calibration circuit is further configured to control the phase of the clock signal according to a shift degree related to the shift direction.

15. The receiver of claim 11, wherein the output circuit is further configured to equalize the digital signal using at least one of Continuous Time Linear Equalization (CTLE), Decision Feedback Equalization (DFE) and Feed-Forward Equalization (FFE).

18. The timing calibration circuit of claim 17, wherein the determination circuit is further configured to change the value of the delay control signal to shift the phase of the clock signal in a first direction when the change in the absolute value decreases, and to change the value of the delay control signal to shift the phase of the clock signal in a second direction opposite to the first direction when the change in the absolute value increases.