Electronic Device and Scan Driving Circuit

2. The electronic device according to claim 1, wherein the switch circuit is a transmission gate circuit, and the electronic device further comprises a second inverter, wherein the output terminal of the first inverter is electrically connected to an input terminal of the second inverter, an output terminal of the second inverter is electrically connected to a first control terminal of the transmission gate circuit, and the output terminal of the first inverter is electrically connected to a second control terminal of the transmission gate circuit.

3. The electronic device according to claim 1, wherein the switch circuit is an N-type transistor, and a control terminal of the N-type transistor is electrically connected to the shift register and the input terminal of the first inverter.

4. The electronic device according to claim 1, wherein the switch circuit is a P-type transistor, and a control terminal of the P-type transistor is electrically connected to the shift register and the output terminal of the first inverter.

7. The electronic device according to claim 1, wherein a control signal received by the input terminal of the buffer through the switch circuit and a scan signal output by the output terminal of the buffer are inverted to each other.

8. The electronic device according to claim 1, wherein the demultiplexer comprises a plurality of scan units, and a plurality of scan signals output by the plurality of scan units are at a high electric potential respectively during different periods to time-divisionally charge a plurality of scan lines.

10. The scan driving circuit according to claim 9, wherein the switch circuit is a transmission gate circuit, and the scan driving circuit further comprises a second inverter, wherein the output terminal of the first inverter is electrically connected to an input terminal of the second inverter, an output terminal of the second inverter is electrically connected to a first control terminal of the transmission gate circuit, and the output terminal of the first inverter is electrically connected to a second control terminal of the transmission gate circuit.

11. The scan driving circuit according to claim 9, wherein the switch circuit is an N-type transistor, and a control terminal of the N-type transistor is electrically connected to the shift register and the input terminal of the first inverter.

12. The scan driving circuit according to claim 9, wherein the switch circuit is a P-type transistor, and a control terminal of the P-type transistor is electrically connected to the shift register and the output terminal of the first inverter.

15. The scan driving circuit according to claim 9, wherein a control signal received by the input terminal of the buffer through the switch circuit and a scan signal output by the output terminal of the buffer are inverted to each other.

16. The scan driving circuit according to claim 9, wherein the demultiplexer comprises a plurality of scan units, and a plurality of scan signals output by the plurality of scan units are at a high electric potential respectively during different periods to time-divisionally charge a plurality of scan lines.