Techniques for Preventing Memory Timing Attacks

3. The apparatus of claim 2, the memory monitor circuitry arranged to identify the request to reload data into the shared memory by a second core of the plurality of cores of the processing device responsive to identifying the active memory attack by the first core.

4. The apparatus of claim 3, the memory monitor circuitry arranged to identify the request to evict data from the shared memory responsive to: a request to evict a portion of data stored in the shared memory by the first core, a request to evict specific data from the shared memory by the first core, a request to evict, by the first core, data from the shared memory associated with the second core, or a memory flush command issued for the shared memory by the first core.

5. The apparatus of claim 3, the memory monitor circuitry arranged to identify the request to fill the shared memory with data by the first core responsive to a request to fill all or substantially of the shared data by the first core.

6. The apparatus of claim 3, the memory monitor circuitry arranged to evict data stored in the shared memory associated with the first core to flush the shared memory responsive to the reload request.

7. The apparatus of claim 1, the memory monitor circuitry arranged to identify a request to reload data from a system memory into the shared memory by the processing device.

8. The apparatus of claim 1, wherein the shared memory comprising a last level cache (LLC).

11. The apparatus of claim 10, the memory monitor logic arranged to identify the request to reload data into the LLC by the second processing core responsive to identifying the active memory attack by the first processing core.

12. The apparatus of claim 11, the memory monitor logic arranged to identify the request to evict data from the LLC responsive to: a request to evict a portion of data stored in the LLC by the first processing core, a request to evict specific data from the LLC by the first processing core, a request to evict data from the LLC associated with the second processing core by the first processing core, or a memory flush command issued for the LLC by the first processing core.

13. The apparatus of claim 11, the memory monitor logic arranged to identify the request to fill the LLC with data by the first processing core responsive to a request to fill all or substantially of the LLC by the first processing core.

14. The apparatus of claim 11, the memory monitor logic arranged to evict data stored in the LLC associated with the first processing core to flush the LLC responsive to the reload request.

15. The apparatus of claim 9, the memory monitor logic arranged to identify a request to reload data from the system memory into the LLC by the second processing core.

16. The apparatus of claim 9, each of the first processing core and the second processing core comprising at least a level 1 cache.

19. The method of claim 18, comprising: identifying the request to reload data into the LLC by the first core responsive to identifying the active memory attack by the second core.

20. The method of claim 18, comprising identifying the request to evict data from the LLC responsive to: a request to evict a portion of data stored in the LLC by the second core, a request to evict specific data from the LLC by the second core, a request to evict data from the LLC associated with the first core by the second core, or a memory flush command issued for the LLC by the second core.

21. The method of claim 18, comprising identifying the request to fill the LLC with data by the second core responsive to a request to fill all or substantially of the LLC by the second core.

22. The method of claim 18, comprising evicting data stored in the LLC associated with the second core to flush the LLC responsive to the reload request.