Stack Management

2. The device of claim 1, wherein the processor includes the first memory, and wherein the second memory is external to the processor.

5. The device of claim 1, wherein the stack manager is further configured to, in response to the particular task returning from a function associated with the frame, execute a return handler that reconfigures the stack manager to transition to the first stack based on the metadata.

6. The device of claim 1, wherein the stack manager is further configured to, in response to the particular task returning from a function associated with the frame, deallocate the second stack from the particular task.

7. The device of claim 6, wherein the stack manager is further configured to, subsequent to deallocating the second stack from the particular task, designate the second stack as available for a next allocation while the second stack is stored in a cache memory.

8. The device of claim 1, wherein each particular tier of stacks includes a pre-determined count of stacks of a pre-determined size, and wherein the pre-determined count and the pre-determined size are associated with a level of the particular tier in the multiple tiers.

10. The method of claim 9, wherein detecting that the size of the frame to be allocated exceeds the available space of the first stack includes detecting an exception caused by a stack limit.

11. The method of claim 10, wherein the selecting, the designating, the copying, and the allocating are performed by an exception handler in the processor in response to the exception.

12. The method of claim 9, further comprising, based at least in part on determining that the size of the frame to be allocated exceeds the available space of the first stack, storing an address of a return handler in a link return register, wherein the frame allocated in the second stack is associated with a function call.

13. The method of claim 12, further comprising, in response to the particular task returning from the function call, executing the return handler corresponding to the address stored in the link return register.

14. The method of claim 9, further comprising, in response to the particular task returning from a function associated with the frame, executing a return handler that reconfigures the stack manager to transition to the first stack based on the metadata.

15. The method of claim 9, further comprising, in response to the particular task returning from a function associated with the frame, deallocating the second stack from the particular task.

16. The method of claim 15, further comprising, subsequent to deallocating the second stack from the particular task, designating the second stack as available for a next allocation while the second stack is stored in a cache memory.

17. The method of claim 14, wherein reconfiguring the stack manager includes copying one or more register values indicated by the metadata to one or more registers to restore a register state.

19. The method of claim 9, wherein the designating of the second stack and the transitioning from the second stack to the first stack are performed independently of a memory management unit.

20. The method of claim 9, wherein the first stack is included in a first memory that has a reduced latency time as compared to a second memory that includes the second stack.

21. The method of claim 20, wherein the first memory includes a tightly coupled memory (TCM).

23. The method of claim 9, further comprising copying arguments of a function from the first stack to the second stack to be accessible via a stack pointer position in the second stack.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions, when executed by the processor, cause the processor to, in response to the particular task returning from a function associated with the frame, execute a return handler that reconfigures the stack manager to transition to the first stack based on the metadata.

26. The non-transitory computer-readable medium of claim 24, wherein the instructions, when executed by the processor, cause the processor to, in response to the particular task returning from a function associated with the frame, deallocate the second stack from the particular task.

27. The non-transitory computer-readable medium of claim 26, wherein the instructions, when executed by the processor, cause the processor to, subsequent to deallocating the second stack from the particular task, designate the second stack as available for a next allocation while the second stack is stored in a cache memory.

28. The non-transitory computer-readable medium of claim 24, wherein each particular tier of stacks includes a pre-determined count of stacks of a pre-determined size, and wherein the pre-determined count and the pre-determined size are associated with a level of the particular tier in the multiple tiers.

30. The apparatus of claim 29, further comprising means for transitioning, at the processor, from the second stack to the first stack in response to detecting that the particular task is returning from a function associated with the frame.