11803326

Implementing a Read Setup Burst Command in 3d NAND Flash Memory to Reduce Voltage Threshold Deviation Over Time

PublishedOctober 31, 2023
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The memory of claim 1, wherein the set of read setup blocks consists of sequential blocks.

3

3. The memory of claim 2, wherein the number represents a number of the sequential read setup blocks and wherein the read setup burst operation includes performing read setup operations on the sequential read setup blocks of the set of read setup blocks starting from the first read setup block, as identified from the address included in the read setup burst command and continuing in sequential order of the sequential read setup blocks until a number of sequential read setup blocks that have had read setup operations performed thereon equals the number, as identified in the read setup burst command.

9

9. The memory of claim 1, wherein the plurality of read setup blocks of the set of read setup blocks are identified in dependence upon their recent use, independent of future read operations.

10

10. The memory of claim 6, wherein the read setup list is generated from a least recently used (LRU) queue that identifies blocks of the memory in dependence upon their use and wherein the read setup list is generated to identify candidate read setup blocks from the LRU queue that have not been accessed for a period of time that exceeds a predetermined threshold.

16

16. The method of claim 12, wherein the set of read setup blocks consists of sequential blocks.

17

17. The method of claim 16, wherein the number represents a number of the sequential read setup blocks and wherein the read setup burst operation includes performing read setup operations on the sequential read setup blocks starting from the first read setup block, as identified from the address included in the read setup burst command, and continuing in sequential order of the sequential read setup blocks until a number of sequential read setup blocks that have had read setup operations performed thereon equals the number, as identified in the read setup burst command.

19

19. The method of claim 12, further comprising maintaining a read setup list of candidate read setup blocks in memory, and wherein the set of read setup blocks includes candidate read setup blocks in the read setup list.

Patent Metadata

Filing Date

Unknown

Publication Date

October 31, 2023

Inventors

Chien-Hsin Liu
Yu-Chih Yeh
Chin-Chu Chung

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “IMPLEMENTING A READ SETUP BURST COMMAND IN 3D NAND FLASH MEMORY TO REDUCE VOLTAGE THRESHOLD DEVIATION OVER TIME” (11803326). https://patentable.app/patents/11803326

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.