Method and Apparatus for Logic Cell-Based Puf Generators

2. The PUF generator of claim 1, further comprising at least two pre-discharge transistors coupled to each of the plurality of columns wherein each of the at least two pre-discharge transistors is coupled between the BL and a first voltage.

3. The PUF generator of claim 2, wherein the at least two access transistors each comprise an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.

4. The PUF generator of claim 2, wherein the at least one enable transistor is coupled between two cross-coupled inverters and a second voltage.

5. The PUF generator of claim 2, wherein the at least two pre-discharge transistors each is coupled between the BL and the first voltage.

6. The PUF generator of claim 2, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.

7. The PUF generator of claim 4, wherein the PUF control circuit is configured to turn on the at least two pre-discharge transistors and the at least two access transistors, and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.

8. The PUF generator of claim 2, wherein the PUF control circuit is configured to turn on the at least one enable transistor, and turn off the at least two access transistors and the at least two pre-discharge transistors of each of the plurality of columns to allow the first metastable logical state to stabilize to the second logical state in each of the plurality of bit cells.

9. The PUF generator of claim 2, wherein the PUF control circuit is further configured to turn on the at least two access transistors to readout the second logical state from each of the plurality of bit cells to generate a PUF signature.

12. The method of claim 11, wherein the at least two access transistors each is coupled between a bitline (BL) and one corresponding storage node.

13. The method of claim 11, wherein the at least two access transistors each comprises an n-type metal oxide semiconductor (NMOS) transistor and the at least one enable transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.

14. The method of claim 11, wherein the at least one enable transistor is coupled between two cross-coupled inverters and a first voltage.

15. The method of claim 11, wherein the at least two pre-discharge transistors each is coupled between the BL and the second voltage.

16. The method of claim 11, wherein the plurality of bit cells each further comprises two cross-coupled inverters each comprising one n-type metal oxide semiconductor (NMOS) and one p-type metal oxide semiconductor (PMOS) transistors.

19. The PUF generator of claim 18, wherein the at least two pre-discharge transistors each is coupled between a bitline (BL) and the first voltage.

20. The PUF generator of claim 18, wherein each of the plurality of bit cells further comprises at least one enable transistor, at least two access transistors, and two cross-coupled inverters, the PUF control circuit is configured to turn on the at least two pre-discharge transistors and the at least two access transistors and to turn off the at least one enable transistor to disable the two cross-coupled inverters to write the first metastable logical state to each of the plurality of bit cells.