Dynamic Random Access Memory (dram) Component for High-Performance, High-Capacity Registered Memory Modules

3. The memory package of claim 1, wherein the package substrate is disposed on a first side of a memory module substrate, wherein a second side of the memory module substrate comprises a second package substrate comprising at least two additional package interfaces and a second dual-ported stack comprising a second plurality of homogeneous memory devices stacked on the second packaged substrate.

4. The memory package of claim 1, wherein the first memory device and the second memory device each comprises steering logic to enable a bypass path through the dual-ported stack.

5. The memory package of claim 1, wherein the first memory device is located at a first side of the dual-ported stack that is disposed on a first surface of the package substrate, and wherein the second memory device is located at a second side of the dual-ported stack that is disposed farthest from the first surface of the package substrate.

6. The memory package of claim 5, wherein the second external data interface connects to the second package interface on the package substrate via wire bonding interconnects.

7. The memory package of claim 1, wherein the second external data interface connects to the second package interface on the package substrate via the first memory device using through-silicon-via (TSV) connections through the plurality of homogeneous memory devices of the dual-ported stack.

8. The memory package of claim 1, wherein the first internal data interface and the second internal data interface are not coupled to the package substrate, wherein the first external data interface and the second external data interface are coupled to the package substrate, and wherein an access to any of the plurality of homogeneous memory devices in the dual-ported stack is made through at least one of the first package interface or the second package interface, wherein the dual-ported stack is operable to transfer data from the first package interface to the second package interface through the first internal data interface and the second internal data interface, and wherein the dual-ported stack is operable to transfer data from the second package interface to the first package interface through the second internal data interface and the first internal data interface.

12. The memory module of claim 9, wherein the first memory device and the second memory device each comprises steering logic to enable a bypass path through the first dual-ported stack.

13. The memory module of claim 9, wherein the first memory device is located at a first side of the first dual-ported stack that is disposed on a first surface of the first package substrate, and wherein the second memory device is located at a second side of the first dual-ported stack that is disposed farthest from the first surface of the first package substrate.

14. The memory module of claim 13, wherein the second external data interface connects to the second package interface on the first package substrate via wire bonding interconnects.

15. The memory module of claim 9, wherein the second external data interface connects to the second package interface on the first package substrate via the first memory device using through-silicon-via (TSV) connections through the plurality of homogeneous memory devices of the first dual-ported stack.

16. The memory module of claim 9, wherein the first internal data interface and the second internal data interface are not coupled to the first package substrate, wherein the first external data interface and the second external data interface are coupled to the first package substrate, and wherein an access to any of the plurality of homogeneous memory devices in the first dual-ported stack is made through at least one of the first package interface or the second package interface, wherein the first dual-ported stack is operable to transfer data from the first package interface to the second package interface through the first internal data interface and the second internal data interface, and wherein the first dual-ported stack is operable to transfer data from the second package interface to the first package interface through the second internal data interface and the first internal data interface.

19. The memory package of claim 18, wherein the set of memory cells are organized as a plurality of bank groups.

20. The memory package of claim 17, wherein the first memory device and the second memory device are dynamic random access memory (DRAM) devices.