Memory Controller System and a Method of Pre-Scheduling Memory Transaction for a Storage Device

2. The system as claimed in claim 1, wherein the variables comprise head and tail representing order of the command buffer in the link.

3. The system as claimed in claim 2, wherein an independent command buffer is placed at the head in the link as first command and a forthcoming command is dependent on tail of the independent command buffer.

4. The system as claimed in claim 2, wherein the commands of the system access to the same address in sequence and access to different banks in parallel.

5. The system as claimed in claim 1, wherein the arbiter determines maximum number of the write or read commands.

7. The method as claimed in claim 6, wherein the arbiter issues the command based on the arbitration policies implemented when there are more than one commands going to a different bank available.

8. The method as claimed in claim 6, wherein the method further comprising the step of snarfing the read commands from write commands if both commands are going to the same address and loading the reads command into a separate command buffer.

9. The method as claimed in claim 6, wherein the method further comprising the step of transacting the write commands and read commands of the same address in sequence, and transacting the write commands and read commands of different banks in any order or in parallel.

10. The method as claimed in claim 6, wherein the method further comprising override autoprecharge command asserted when the linked-list controller has future command being linked with the current command.

11. The method as claimed in claim 10, wherein the linked-list controller set autoprecharge low for a continuous row access.

12. The method as claimed in claim 10, wherein the linked-list controller set autoprecharge high for a row switch.

13. The method as claimed in claim 10, wherein the linked-list controller preserves the autoprecharge instruction when row continuity information is absent.