11836096

Memory-Flow Control Register

PublishedDecember 5, 2023
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
8 claims

Legal claims defining the scope of protection, as filed with the USPTO.

10

10. The method of claim 1, wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.

11

11. The method of claim 1, wherein the controller comprises a CXL controller.

14

14. The method of claim 12, wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.

24

24. The apparatus of claim 15, wherein the interconnect is configured to comport with at least one CXL standard.

25

25. The apparatus of claim 15, wherein the controller comprises a CXL controller.

28

28. The apparatus of claim 26, wherein the interconnect is configured to comport with at least one CXL standard.

29

29. The apparatus of claim 26, wherein the CXL memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device.

36

36. The apparatus of claim 15, wherein the controller determines the number of memory requests that are serviceable by the CXL memory device based on a quantity of memory requests that are serviceable by the CXL memory device while providing a specified performance parameter defined by a quality of service (QoS) parameter.

Patent Metadata

Filing Date

Unknown

Publication Date

December 5, 2023

Inventors

Nikesh Agarwal
Robert Walker
Laurent Isenegger

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Cite as: Patentable. “Memory-Flow Control Register” (11836096). https://patentable.app/patents/11836096

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