Asynchronous Interrupt Event Handling in Multi-Plane Memory Devices

2. The memory device of claim 1, wherein the command result signal and the persistent event register signal are provided to at least one of a memory sub-system controller or a host system coupled to the memory device.

3. The memory device of claim 2, wherein the persistent event register signal is to notify the at least one of the memory sub-system controller or the host system that the memory device has recovered from the occurrence of the asynchronous interrupt event and that the plurality of asynchronous memory access operations were terminated.

5. The memory device of claim 2, wherein detecting the occurrence of the asynchronous interrupt event comprises at least one of receiving a reset command from the at least one of the memory sub-system controller or the host system, or detecting a drop in a voltage supply level of the memory device.

6. The memory device of claim 1, wherein the command result signal and the persistent event register signal are asserted based on a value stored in a device status register representing a state of the plurality of asynchronous memory access operations on each of the plurality of memory planes.

7. The memory device of claim 1, wherein performing the plurality of asynchronous memory access operations comprises performing a respective one of the plurality of asynchronous memory access operations on each of the plurality of memory planes concurrently.

8. The memory device of claim 1, wherein initiating the termination procedure for each of the plurality of asynchronous memory access operations comprises causing a respective state machine associated with a respective one of the plurality of memory planes to enter one or more states to terminate a corresponding one of the plurality of asynchronous memory access operations being performed on the respective one of the plurality of memory planes.

12. The method of claim 11, wherein the command result signal and the persistent event register signal are provided to at least one of a memory sub-system controller or a host system coupled to the memory device.

13. The method of claim 12, wherein the persistent event register signal is to notify the at least one of the memory sub-system controller or the host system that the memory device has recovered from the occurrence of the asynchronous interrupt event and that the plurality of asynchronous memory access operations were terminated.

15. The method of claim 12, wherein detecting the occurrence of the asynchronous interrupt event comprises at least one of receiving a reset command from the at least one of the memory sub-system controller or the host system, or detecting a drop in a voltage supply level of the memory device.

16. The method of claim 11, wherein the command result signal and the persistent event register signal are asserted based on a value stored in a device status register representing a state of the plurality of asynchronous memory access operations on each of the plurality of memory planes.

17. The method of claim 11, wherein performing the plurality of asynchronous memory access operations comprises performing a respective one of the plurality of asynchronous memory access operations on each of the plurality of memory planes concurrently.

18. The method of claim 11, wherein initiating the termination procedure for each of the plurality of asynchronous memory access operations comprises causing a respective state machine associated with a respective one of the plurality of memory planes to enter one or more states to terminate a corresponding one of the plurality of asynchronous memory access operations being performed on the respective one of the plurality of memory planes.