Encrypted Data Processing Design Including Local Buffers

2. The method of claim 1, wherein a tag within each register entry of the register file indicates whether data is in ciphertext or plaintext.

3. The method of claim 2, wherein only data from register entries having the tag indicating that the data is in ciphertext within the register file are decrypted and stored within the local buffer of the functional unit and wherein only data from register entries having the tag indicating that the data is in ciphertext within the register file are encrypted and stored back to the register file.

4. The method of claim 1, wherein prior to processing by the functional unit, a reference thread identification (ID) provided by a processor is matched with a stored secure thread ID within the functional unit.

5. The method of claim 4, wherein the stored secure thread ID and reference thread ID are linked to the encryption key of a data owner and a hash of a program being executed by a hardware thread signed by an application author.

6. The method of claim 4, wherein the processing is not performed when the reference thread ID and the stored secure thread ID do not match.

7. The method of claim 1, wherein a coherency protocol is configured to maintain consistency between data of the local buffer of the functional unit and data of the register file.

8. The method of claim 7, wherein the coherency protocol further maintains consistency between a plurality of additional local buffers of respective functional units and data of the register file.

10. The processor of claim 9, wherein a tag within each register entry of the register file indicates whether data is in ciphertext or plaintext.

11. The processor of claim 10, wherein only data from register entries having the tag indicating that the data is in ciphertext within the register file are decrypted by the decryption module and stored within the local buffer of the functional unit.

12. The processor of claim 9, wherein prior to processing by the functional unit, a reference thread identification (ID) provided by the processor is matched with a stored secure thread ID within the functional unit.

13. The processor of claim 12, wherein the stored secure thread ID and reference thread ID are linked to the encryption key of a data owner and a hash of a program being executed by a hardware thread signed by an application author.

14. The processor of claim 12, wherein the processing is not performed when the reference thread ID and the stored secure thread ID do not match.

15. The processor of claim 9, wherein a coherency protocol is configured to maintain consistency between data of the local buffer of the functional unit and data of the register file.

18. The processor of claim 17, wherein the secure thread ID is derived from a cryptographic hash function of a program being executed by a hardware thread.

19. The processor of claim 16, wherein the encryption key is used to encrypt cleartext data processed from the local buffer for storage back to the register file.