Method for Latency Detection on a Hardware Simulation Accelerator

2. The method according to claim 1, wherein the target latency value is based on an existing idle latency test.

3. The method according to claim 2, wherein the target latency value is a defined percentage below a performance latency result per transaction of said existing idle latency test.

4. The method according to claim 1, wherein the replacing is performed responsive to determining that the measured latency is a defined percentage above the previous measured latency.

5. The method according to claim 1, wherein said latency is measured in processor clock cycles taken to complete the individual transaction.

6. The method according to claim 1 wherein the application is a workload software application or an exerciser.

9. The computer system of claim 8, wherein the target latency value is based on an existing idle latency test.

10. The computer system of claim 9, wherein the target latency value is a defined percentage below a performance latency result per transaction of said existing idle latency test.

11. The computer system of claim 8, wherein the replacing is performed responsive to determining that the measured latency is a defined percentage above the previous measured latency.

12. The computer system of claim 8, wherein said latency is measured in processor clock cycles taken to complete the individual transaction.

13. The computer system of claim 8 wherein the application is a workload software application or an exerciser.

14. The computer system of claim 8 wherein the first and second checkpoints are saved as a pair.