Memory Array, Memory Structure and Operation Method of Memory Array

2. The memory array according to claim 1, wherein the memory array is a computational memory array, and configured to perform a matrix-vector multiplication (MVM) operation.

3. The memory array according to claim 2, wherein the electrically programmable NVMs are configured to be programmed with various conductances.

4. The memory array according to claim 2, wherein the capacitors of the memory cells have substantially identical capacitance.

5. The memory array according to claim 2, wherein the bit lines are configured to receive voltage pulses with various amplitudes during the MVM operation.

6. The memory array according to claim 5, wherein the voltage pulses have substantially identical pulse width.

7. The memory array according to claim 2, wherein output currents as results of the MVM operation are provided from first source/drain terminals of the floating gate transistors.

8. The memory array according to claim 7, wherein each of the output currents shows a non-linear characteristic with respect to variation of a voltage at the gate terminal of the corresponding floating gate transistor.

12. The memory structure according to claim 11, wherein a second source/drain structure of the write transistor in each memory cell is electrically connected to a signal line lying over the write transistor.

13. The memory structure according to claim 11, wherein a top electrode of the capacitor in each memory cell is electrically connected to a floating gate of a floating gate transistor.

14. The memory structure according to claim 11, wherein the electrically programmable NVM and the capacitor in each memory cell is embedded in a dielectric structure covering the write transistor.

15. The memory structure according to claim 11, wherein a resistance adjustable layer of the electrically programmable NVM in each memory cell is a dielectric layer or a phase change layer.

17. The operation method of the memory array according to claim 16, wherein the capacitors have substantially identical capacitance.

18. The operation method of the memory array according to claim 16, wherein the voltage pulses have substantially identical pulse width, and have various amplitudes.

19. The operation method of the memory array according to claim 16, wherein the write transistors are switched off after the capacitors are fully discharged after programming the electrically programmable NVMs and before performing the MVM cycle.

20. The operation method of the memory array according to claim 16, wherein the write transistors are turned off during providing the voltage pulses to the electrically programmable NVMs, and are switched on while discharging the capacitors in the MVM cycle.