Receiver Side Setup and Hold Calibration

6. The method of claim 1, wherein the calibrating the local clock signals is based on the IO of the set of IOs that is last to receive the respective local clock signal.

7. The method of claim 1, wherein the calibrating the local clock signals is based on a set of multi-delay circuits that each include a first delay circuit that delays the respective local clock signal by a first delay time and a second delay circuit that delays the respective local clock signal by a second delay time, wherein the second delay time is shorter than the first delay time.

8. The method of claim 1, wherein each IO of the set of IOs is associated with a different timing of the respective local clock signal and the respective local clock signal is calibrated for each IO of the set of IOs in parallel.

14. The apparatus of claim 9, wherein the calibrating the local clock signals is based on the IO of the set of IOs that is last to receive the respective local clock signal.

15. The apparatus of claim 9, wherein the calibrating the local clock signals is based on a set of multi-delay circuits that each include a first delay circuit that delays the respective local clock signal by a first delay time and a second delay circuit that delays the respective local clock signal by a second delay time, wherein the second delay time is shorter than the first delay time.

17. The system of claim 16, wherein the set of multi-delay circuits are calibrated based on a total number of first delays associated with the first delay time determined based on a data window of the latched data signal and a total number of second delays associated with the second delay time determined based on the data window of the latched data signal and the total number of first delays.

18. The system of claim 17, wherein the total number of first delays is based on a minimum number of first delays associated with the first delay time that exceeds the data window of the latched data signal, wherein the number of first delays is one less than the minimum number of first delays.

19. The system of claim 17, wherein the set of multi-delay circuits are calibrated further based on a number of first delays associated with the first delay time to align the clock edges of the local clock signals with a middle of the data window and a number of second delays associated with the second delay time to align the clock edges of the local clock signals with the middle of the data window.

20. The system of claim 17, wherein each IO circuit of the set of IO circuits is associated with a different timing of the local clock signals and the set of multi-delay circuits are calibrated for each IO circuit of the set of IO circuits in parallel.