Gate Driving Circuit and Display Panel

2. The gate driving circuit of claim 1, wherein, the pull-up node is configured to provide a pull-up control signal including at least one step pulse, wherein each step pulse of the at least one step pulse includes a first potential pulse and a second potential pulse in succession, and a potential of the first potential pulse is lower than a potential of the second potential pulse.

3. The gate driving circuit of claim 2, wherein, each step pulse of the at least one step pulse further includes a third potential pulse following the second potential pulse, the potential of the second potential pulse being lower than a potential of the third potential pulse.

4. The gate driving circuit of claim 1, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

5. The gate driving circuit of claim 4, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

9. A display panel, comprising the gate driving circuit according to claim 1.

10. A display panel, comprising the gate driving circuit according to claim 8.

11. The gate driving circuit of claim 8, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

12. The gate driving circuit of claim 11, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

13. The display panel of claim 9, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

14. The display panel of claim 13, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

15. The display panel of claim 10, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

16. The display panel of claim 15, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.