Device and Method for Testing a Sequence Generated by a Random Number Generator

2. The device of claim 1, wherein the comparator is configured to output a validation bit for a statistical test, if each sum value is strictly superior to the associated lower threshold and strictly inferior to the higher threshold.

3. The device of claim 2, wherein the validation unit is configured to reject the bit sequence if at least one sum value for a statistical test is inferior or equal to the associated lower threshold or superior or equal to the corresponding higher threshold.

7. The device of claim 1, wherein the bit sequence length N is changed between one or more clock cycles.

8. The device of claim 1, wherein a new value for the error probability and the number N may be received at different times or simultaneously.

11. A system implemented on at least one integrated circuits, said system comprising a device using a random bit sequence generated by a random number generator, wherein said device further comprises a testing device according to claim 1 for testing each random bit sequence generated by said random number generator.