Information Processing Device

2. The information processing device according to claim 1, wherein the counter value to be input in synchronization to the selector is different between all the hash computation circuits at the same time.

3. The information processing device according to claim 1, wherein the interconnect is configured by a plurality of routers connected in butterfly connection.

4. The information processing device according to claim 3, wherein the interconnect has stages number of which is equal to number of bits when number of the banks is represented in binary.

5. The information processing device according to claim 4, wherein the interconnect connects each of the hash computation circuits and one of the banks in the memory to each other based on bank specifying information included in a corresponding one of the read requests, to supply the read requests to the banks in the memory.

6. The information processing device according to claim 5, wherein the interconnect connects each of the hash computation circuit and the memory based on a hash computation circuit number included in the read requests, to supply data read from the memory to one of the hash computation circuits having the hash computation circuit number.