Analysis of Events in an Integrated Circuit Using Cause Tree and Buffer

2. The IC according to claim 1, wherein the one or more functional hardware circuits are to process communication packets.

3. The IC according to claim 1, wherein the buffer analysis circuit is to produce a histogram of fill levels of the memory buffer.

4. The IC according to claim 1, wherein the buffer analysis circuit is to produce a histogram of waiting times of the events in the memory buffer.

5. The IC according to claim 1, wherein the buffer analysis circuit is to track a performance metric of the memory buffer, and to provide the performance metric for analysis by an external device.

7. The method according to claim 6, wherein the one or more functional hardware circuits process communication packets.

8. The method according to claim 6, wherein analyzing the performance of the cause-tree circuit comprises producing a histogram of fill levels of the memory buffer.

9. The method according to claim 6, wherein analyzing the performance of the cause-tree circuit comprises producing a histogram of waiting times of the events in the memory buffer.

10. The method according to claim 6, wherein analyzing the performance of the cause-tree circuit comprises tracking a performance metric of the memory buffer, and providing the performance metric for analysis by an external device.

12. The electronic circuit according to claim 11, wherein the cause-tree circuit comprises leaf nodes, middle nodes and a root node, the leaf nodes comprising the storage elements to collect the events from the one or more functional hardware circuits, the middle nodes comprising the coalescing circuits to coalesce the collected events and to deliver the events to the root node, and the root node to buffer the events in the memory buffer.

13. The electronic circuit according to claim 11, wherein the one or more functional hardware circuits are to process communication packets.

14. The electronic circuit according to claim 11, wherein the buffer analysis circuit is to produce a histogram of fill levels of the memory buffer.

15. The electronic circuit according to claim 11, wherein the buffer analysis circuit is to produce a histogram of waiting times of the events in the memory buffer.

16. The electronic circuit according to claim 11, wherein the buffer analysis circuit is to track a performance metric of the memory buffer, and to provide the performance metric for analysis by an external device.