Method and System for Overlapping Sliding Window Segmentation of Image Based on FPGA

2. The method according to claim 1, wherein during the vertical overlapping sliding window process and segmentation in step S6, the next batch of segmented sub-images and a previous batch of segmented sub-images are respectively stored in a same corresponding BRAM of the BRAMs, and (k−s)*k pixel data in the overlapping area formed by the vertical overlapping sliding window process are spliced with subsequent pixel data in the off-chip DDR memory by starting address rollback offset, thereby realizing data reuse in a vertical overlapping area.

3. The method according to claim 1, wherein the preset threshold in step S2 is equal to a maximum capacity of burst continuous writing, in such a manner that a highest access efficiency to the off-chip DDR is achieved.

4. The method according to claim 1, wherein internal pixel data of each segmented sub-image written in the off-chip DDR memory in step S8 are continuously addressed in row-major order, and respective segmented sub-images are sorted in column-major order with continuous addresses, that is, the sub-images are stored in an order of (0,0), (1,0), (2,0), . . . , (┌m/s┐−1,0), (0,1), (1,1), . . . , (┌m/s┐−1, ┌n/s┐−1).

5. A system, comprising one or more processors for implementing the method according to claim 1.

6. A non-transitory computer-readable storage medium, wherein a program is stored thereon, and when executed by a processor, the program implements the method according to claim 1.