11982987

Programmable Logic Controller and Analyzer

PublishedMay 14, 2024
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
12 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The programmable logic controller according to claim 1, wherein the identification section further identifies an abnormal device by analyzing a deviation between the time-series data of each of the devices collected by the collection section and time-series data at a normal time by using the detection algorithm determined by the determination section in accordance with a user instruction or periodically.

4

4. The programmable logic controller according to claim 1, wherein upon reception of a user instruction for an arbitrary device, the classification section classifies the device in accordance with the user instruction.

5

5. The programmable logic controller according to claim 1, wherein when a value collected in a previous scan cycle and a value collected in a current scan cycle in a group of one or more devices have not changed in all the devices of the group as a collection target, the collection section deletes the value collected in the current scan cycle and compresses the collected time-series data.

6

6. The programmable logic controller according to claim 1, wherein the determination section excludes time-series data classified by the classification section as the device in which a value changes irregularly, to determine a detection algorithm used in identification of an abnormality.

7

7. The programmable logic controller according to claim 1, wherein the identification section identifies an abnormal device by performing analysis, using an evaluation variable used for analysis of the abnormal device and a parameter corresponding to the evaluation variable on a basis of a type of the time-series data classified by the classification section as the detection algorithm.

9

9. The programmable logic controller according to claim 1, wherein the identification section compares the detection algorithm determined by the determination section with a characteristic of time-series data corresponding to the detection algorithm and performs the identification as an abnormal device when a difference exceeds a predetermined threshold.

11

11. The programmable logic controller according to claim 1, further comprising an output section for outputting, as an identification result, a candidate device having a possibility of abnormality in a distinguishable manner.

12

12. The programmable logic controller according to claim 11, wherein the output section displays, as the identification result, each of the devices on a display part in order of an abnormality degree indicating a size of the abnormality or in order of an occurrence time of the abnormality.

13

13. The programmable logic controller according to claim 11, wherein the output section displays, as the identification result, time-series data at a normal time of the device identified as an abnormal device and time-series data at a time of abnormality on the display part in a comparable manner.

14

14. The programmable logic controller according to claim 1, wherein the time-series data collected by the collection section includes image data.

15

15. The programmable logic controller according to claim 1, wherein a characteristic of the time-series data is a characteristic related to periodicity or continuity.

18

18. The programmable logic controller according to claim 1, further comprising a memory card that temporarily holds the time-series data of the device collected by the collection section before the time-series data is used by the classification section and the identification section.

Patent Metadata

Filing Date

Unknown

Publication Date

May 14, 2024

Inventors

Tetsuya MIYASAKA

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Cite as: Patentable. “PROGRAMMABLE LOGIC CONTROLLER AND ANALYZER” (11982987). https://patentable.app/patents/11982987

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