Legal claims defining the scope of protection, as filed with the USPTO.
2. The apparatus of claim 1, wherein the AI accelerator is further configured to receive the indication of the failure of a block of the plurality of memory devices.
3. The apparatus of claim 1, wherein the AI accelerator is further configured to receive the indication of the failure of a word line of the plurality of memory devices.
4. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust a ratio of parity elements to storage elements.
5. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to refrain from utilizing blocks of the plurality of memory devices.
6. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust a quantity of bits that each of a plurality of memory cells can store.
7. The apparatus of claim 6, wherein the plurality of memory devices are configured to adjust the quantity of bit that each of the plurality of memory cells can store from a single-level cell (SLC) to a multi-level cell (MLC).
8. The apparatus of claim 6, wherein the plurality of memory devices are configured to adjust the level of the plurality of memory cells from a multi-level cell (MLC) to a single-level cell (SLC).
9. The apparatus of claim 1, wherein the AI accelerator is further configured to generate the data protection scheme adjustment utilizing an artificial neural network (ANN).
10. The apparatus of claim 1, wherein the AI accelerator configured to generate the data protection scheme adjustment is further configured to select the data protection scheme adjustment by comparing the failure data to a plurality of signatures comprising failure data using a table.
12. The apparatus of claim 1, wherein the failure data includes latency data, read latency data, erase latency data, and raw bit error rates (RBERs).
15. The method of claim 14, wherein the data protection scheme adjustment tightens data protection scheme coverage in the memory device and the different data protection scheme adjustment loosens redundant array of independent NAND (RAINS coverage in the memory device.
17. The apparatus of claim 16, wherein the AI accelerator is configured to receive the data corresponding to a passing or failing condition of a block or a word line of the memory device.
18. The apparatus of claim 16, wherein the AI accelerator is configured to generate the data protection scheme adjustment for a block or word line of the memory device.
21. The system of claim 20, wherein the AI accelerator is further configured to generate a summary report for failures of a stripe of the plurality of memory devices described in the state data that are not adjusted by the data protection scheme adjustment.
22. The system of claim 21, wherein the AI accelerator is further configured to provide the summary report including the state data for including in a pool of unsupported failures.
23. The system of claim 22, wherein the pool of unsupported failures is utilized for fabricating and testing NAND memory devices.
24. The system of claim 20, wherein the data protection scheme is a redundant array of independent NAND (RAIN).
Unknown
May 21, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.