11995529

Lossless Tiling in Convolution Networks - Tiling Configuration for a Sequence of Sections of a Graph

PublishedMay 28, 2024
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
12 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The data processing system of claim 1, wherein the first topology of tiling configurations is determined based on a number of processing nodes in the first section.

3

3. The data processing system of claim 1, wherein the first topology of tiling configurations is determined based on respective processing logics implemented by respective processing nodes in the first section.

4

4. The data processing system of claim 1, wherein the first topology of tiling configurations is determined based on a size of the inputs of the first section.

5

5. The data processing system of claim 1, wherein the first topology of tiling configurations is determined based on a size of the final outputs of the first section.

6

6. The data processing system of claim 1, wherein the second topology of tiling configurations is determined based on one or more of (i) a number of processing nodes in the second section, (ii) respective processing logics implemented by respective processing nodes in the second section, (iii) on a size of the inputs of the second section, and (iv) a size of the final outputs of the second section.

7

7. The data processing system of claim 1, wherein the sequence of sections includes at least a third section, wherein the compile time logic is further configured to configure the third section with a third topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the third section, wherein the third topology of tiling configurations is different from the first topology of tiling configurations and the second topology of tiling configurations; and wherein the runtime logic is further configured to execute the third section to generate the inputs, intermediate outputs, and final outputs of the third section in the third topology of tiling configurations.

8

8. The data processing system of claim 1, wherein the first topology of tiling configurations includes respective tiling configurations for the inputs, intermediate outputs, and final outputs of the first section.

9

9. The data processing system of claim 1, wherein the graph is a convolutional neural network, wherein sections in the sequence of sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are input gradients, and wherein the inputs, intermediate outputs, and final outputs of the second section are input gradients.

10

10. The data processing system of claim 1, wherein the final outputs of the first section have a non-overlapping final tiling configuration, the intermediate outputs of the first section have corresponding one or more overlapping intermediate tiling configurations, and the input of the first section has an overlapping input tiling configuration.

15

15. The method of claim 12, wherein the first topology of tiling configurations includes respective tiling configurations for the inputs, intermediate outputs, and final outputs of the first section.

16

16. The method of claim 12, wherein the graph is a convolutional neural network, sections in the sequence of sections are forward pass subgraphs, wherein the sections are backward pass subgraphs, wherein the inputs, intermediate outputs, and final outputs of the first section are image data, wherein the inputs, intermediate outputs, and final outputs of the second section are image data.

19

19. The non-transitory computer readable storage medium of claim 18, wherein the final outputs of the first section have a non-overlapping final tiling configuration, the intermediate outputs of the first section have corresponding one or more overlapping intermediate tiling configurations, and the input of the first section has an overlapping input tiling configuration.

Patent Metadata

Filing Date

Unknown

Publication Date

May 28, 2024

Inventors

Tejas Nagendra Babu NAMA
Ruddhi CHAPHEKAR
Ram SIVARAMAKRISHNAN
Raghu PRABHAKAR
Sumti JAIRATH
Junjue WANG
Kaizhao LIANG
Adi FUCHS
Matheen MUSADDIQ
Arvind Krishna SUJEETH

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Cite as: Patentable. “Lossless Tiling in Convolution Networks - Tiling Configuration for a Sequence of Sections of a Graph” (11995529). https://patentable.app/patents/11995529

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