Precise Time Management Using Local Time Base

3. The apparatus of claim 2, wherein the update circuit, in updating the value of the first local timebase, is configured to increment the first local timebase at the standard increment size in response to determining, at a third instance of the synchronization event, that the first local timebase is not saturated and is not lagging the global timebase by more than a limit value.

6. The apparatus of claim 5, wherein the adjustment factor corresponds to a latency for synchronizing the initial timebase limit to the adjusted timebase limit across a boundary between a first clock domain that operates according to the first clock signal and a second clock domain that operates according to the second clock signal, wherein the latency is measured in a number of periods of the first clock signal.

7. The apparatus of claim 1, further comprising a synchronization circuit coupled to receive the first and second clock signals, wherein the synchronization circuit is configured to, once every N cycles of the first clock signal, output a control signal synchronized to the second clock signal to cause an instance of the synchronization event.

9. The apparatus of claim 8, wherein the peripheral control circuit is configured to cause the peripheral interface circuit to conduct one or more exchanges with the first integrated circuit in order to correlate the first local timebase to the global timebase, and further configured to determine the correlation between the second local timebase to the first local timebase in response to completing the correlation between the first local timebase and the global timebase.

12. The method of claim 11, further comprising incrementing the first local timebase at the standard increment size in response to determining, at a third instance of the synchronization event, that the first local timebase is not saturated and is not lagging the global timebase by more than a limit value.

15. The method of claim 14, wherein the adjustment factor corresponds to a latency for synchronizing the initial timebase limit to the adjusted timebase limit across a boundary between a first clock domain that operates according to the first clock signal and a second clock domain that operates according to the second clock signal, wherein the latency is measured in a number of periods of the first clock signal.

17. The system of claim 16, wherein the peripheral interface circuit is configured to operate according to a third clock signal and wherein the peripheral control circuit is configured to operate according to a fourth clock signal, and wherein the peripheral control circuit is further configured to maintain the second local timebase based on phase and frequency differences of the third and fourth clock signals.

20. The system of claim 16, wherein the peripheral control circuit is configured to cause the peripheral interface circuit to conduct one or more exchanges with the host circuit in order to correlate the first local timebase to the global timebase, and further configured to determine the correlation between the second local timebase to the first local timebase in response to completing the correlation between the first local timebase and the global timebase.