12038809

Failure Analysis for Uncorrectable Error Events

PublishedJuly 16, 2024
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
14 claims

Legal claims defining the scope of protection, as filed with the USPTO.

4

4. The method of claim 2, wherein the plurality of error types includes a first error type for address translation corruption, a second error type for physical address corruption or memory defect, and a third error type for reliability failure.

6

6. The method of claim 5, wherein the de-scrambling is performed using a pseudo-random seed generated from a physical address associated with the given logical address.

7

7. The method of claim 5, wherein the plurality of error types includes an error type for address translation corruption.

8

8. The method of claim 7, wherein the address translation corruption is determined to have occurred when the initial checksum is less than a parity threshold, the decoder status indicates that the error correction decoding is successful, and the given logical address does not match the decoded logical address.

9

9. The method of claim 5, wherein the plurality of error types includes an error type for physical address corruption or memory defect.

10

10. The method of claim 9, wherein the physical address corruption or the memory defect is determined to have occurred when the decoder status indicates that the error correction decoding has failed, and the initial checksum is greater than a parity threshold.

11

11. The method of claim 5, wherein the plurality of error types includes an error type for reliability failure.

12

12. The method of claim 11, wherein the reliability failure is determined to have occurred when the decoder status indicates that the error correction decoding has failed, and the initial checksum is less than a parity threshold.

13

13. The method of claim 5, wherein the error correction decoding is performed using a low-density parity-check (LDPC) code.

16

16. The storage device of claim 14, wherein the plurality of error types includes a first error type for address translation corruption, a second error type for physical address corruption or memory defect, and a third error type for reliability failure.

17

17. The storage device of claim 16, wherein the first error type is determined to have occurred when the initial checksum is less than a parity threshold, the decoder status indicates that the error correction decoding is successful, and the given logical address does not match the decoded logical address.

18

18. The storage device of claim 16, wherein the second error type is determined to have occurred when the decoder status indicates that the error correction decoding has failed, and the initial checksum is greater than a parity threshold.

19

19. The storage device of claim 16, wherein the third error type is determined to have occurred when the decoder status indicates that the error correction decoding has failed, and the initial checksum is less than a parity threshold.

20

20. The storage device of claim 14, wherein the error correction code is a low-density parity-check (LDPC) code, and wherein a parity threshold used for determining which error type is based on a maximum number of parity bits used for the LDPC code.

Patent Metadata

Filing Date

Unknown

Publication Date

July 16, 2024

Inventors

Fan Zhang
ShiangJyh Steve Chang

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Cite as: Patentable. “FAILURE ANALYSIS FOR UNCORRECTABLE ERROR EVENTS” (12038809). https://patentable.app/patents/12038809

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