Wiring Structure of Pixel Driving Circuit, Display Panel, and Display Device

2. The wire layout of the pixel driving circuit according to claim 1, wherein the pixel driving circuit further comprises the storage capacitor, the first node is connected to a first plate of the storage capacitor through a first wire, and the second node is to a second plate of the storage capacitor through a second wire.

3. The wire layout of the pixel driving circuit according to claim 2, wherein the scan signal line does not overlap with the first wire and the second wire.

4. The wire layout of the pixel driving circuit according to claim 1, wherein a distance between the data signal line and a side of the second portion of the first power signal line away from the data signal line is greater than a distance between the data signal line and a side of the first portion of the first power signal line away from the data signal line.

5. The wire layout of the pixel driving circuit according to claim 1, wherein an active layer of the second switching element and an active layer of the driving transistor are formed integrally, and the second switching element and the driving transistor are arranged adjacently.

6. The wire layout of the pixel driving circuit according to claim 1, wherein the pixel driving circuit further comprises a fourth switching element and an eighth switching element, the fourth switching element and the eighth switching element are arranged at a same side of the driving transistor, and an active layer of the fourth switching element and an active layer of the eighth switching element are formed integrally.

7. The wire layout of the pixel driving circuit according to claim 6, wherein the fourth switching element is configured to write an initialization signal to the second node, and the eighth switching element is configured to write the initialization signal to an anode of a light emitting device connected to the pixel driving circuit.

10. The wire layout of the pixel driving circuit according to claim 8, wherein the pixel driving circuit further comprises a first capacitor, and an orthographic projection of the first capacitor on a base substrate does not overlap with an orthographic projection of the storage capacitor on the base substrate.

12. The wire layout of the pixel driving circuit according to claim 11, wherein the first capacitor is adjacent to the storage capacitor.

14. The wire layout of the pixel driving circuit according to claim 10, wherein the first capacitor and the storage capacitor are arranged between the first switching element and the eighth switching element.

15. The wire layout of the pixel driving circuit according to claim 11, wherein one of the first plate and the second plate of the first capacitor and one of the first plate and the second plate of the storage capacitor are made of a same metal layer.

16. The wire layout of the pixel driving circuit according to claim 11, wherein the first power signal line and the data signal layer are arranged in a same layer, and a via is provided in the second power signal line.

17. A display panel, comprising the wire layout of the pixel driving circuit according to claim 1.

18. A display device, comprising the display panel of claim 17.