Method and Apparatus for Processing Convolution Operation in Neural Network Using Sub-Multipliers

2. The method of claim 1, wherein the first-bit feature map operands are pixel values at different pixel locations in an input feature map.

12. The method of claim 1, further comprising clock-gating a multiplication operation of a sub-multiplier to which a zero operand is dispatched, for zero skipping, in response to the zero operand being present in the m×n operand pairs.

13. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1.

14. The method of claim 1, wherein the generating of the m x n outputs by performing the addition and accumulation operations includes using an adder and an accumulator included in the convolution operator.

15. The method of claim 1, wherein a product of the first-bit and the second-bit is equal to a product of k and a total number of the sub-multipliers.

16. The method of claim 1, wherein the sub-multipliers is a sub-multiplier that is decomposed from the k-bit multiplier to have a selected bit precision that is less than a full bit precision of the k-bit multiplier.

17. The method of claim 16, wherein the selected bit precision is determined based on a bit precision of at least one operand of an operand pair, of the operand pairs.

21. The apparatus of claim 20, wherein the first-bit feature map operands are pixel values at different pixel locations in an input feature map.

23. The apparatus of claim 20, wherein the first-bit feature map operands are pixel values at corresponding pixel locations in different input feature maps, wherein the different input feature maps correspond to different input channels.

29. The apparatus of claim 20, wherein the processor is further configured to, clock-gate a multiplication operation of a sub-multiplier to which a zero operand is dispatched, for zero skipping, in response to a zero operand being present in the m x n operand pairs.