CPU Cache Flushing to Persistent Memory

2. The system of claim 1, wherein the write commands are flushed during an asynchronous memory refresh sequence.

3. The system of claim 2, wherein the write commands are moved to the protected write queue from at least one cache of a processing device of the host system.

4. The system of claim 1, wherein software ensures that stores prior to a store fence instruction are globally visible in the host system before any store after the store fence instruction becomes globally visible in the host system.

5. The system of claim 1, wherein software executing on the host system moves the write commands to the protected write queue prior to retiring stores to be persisted by the host system.

6. The system of claim 1, wherein the impending loss of power is detected when a supply voltage obtained from the power supply falls below a predetermined threshold.

7. The system of claim 1, wherein the power supply monitor is external to the host system.

8. The system of claim 1, wherein the first data is stored in the memory component less than 20 ms after the host system receives the signal from the power supply monitor.

9. The system of claim 1, wherein the first data is stored in the memory component using power supplied by the at least one capacitor.

10. The system of claim 1, further comprising a cache configured to receive the write commands.

11. The system of claim 10, wherein the cache comprises volatile memory, and the first data is stored in non-volatile memory.

13. The system of claim 12, wherein the at least one capacitor provides at least 10 ms of holdup time.

14. The system of claim 12, further comprising, responsive to detecting the loss of power, generating a log associated with storing the data.