Memory Sub-System Addressing for Data and Additional Data Portions

4. The method of claim 3, wherein the metadata comprises a host poison bit and a memory device poison bit.

5. The method of claim 1, wherein the page comprises a plurality of portions of data, each of the plurality of portions of data are 64 bytes in size.

6. The method of claim 5, wherein the plurality of portions of data are consecutively stored in the page and a plurality of portions of additional data associated with each of the plurality of portions of data are consecutively stored in the page.

8. The apparatus of claim 7, wherein the portion of data is 64 bytes in size.

9. The apparatus of claim 7, wherein the page associated with the portion of data is 2048 bytes in size.

10. The apparatus of claim 7, wherein the sector in the memory device comprises 512 entries and an entry is 64 bytes of data.

11. The apparatus of claim 10, wherein each of the 512 entries comprises at least 3 bytes of CRC data.

12. The apparatus of claim 7, wherein the memory device is a Compute Express Link (CXL) compliant memory device.

13. The apparatus of claim 7, further comprising a ferroelectric field-effect transistor (FeFET) memory device, a dynamic random-access memory (DRAM), ferroelectric random-access memory (FeRAM), or a resistive random-access memory (ReRAM) device, or any combination thereof.

15. The system of claim 14, wherein the sector spans at least two rows of memory cells within the memory array.

16. The system of claim 15, wherein an additional sector begins at an off-set from a beginning of a row of memory cells that the sector terminates in.

17. The system of claim 14, wherein the memory controller is to receive address bits associated with the portion of data, wherein a first portion of the address bits indicates a particular sector, a particular channel, and a particular offset associated with the location of the portion of data.

18. The system of claim 14, wherein the memory controller is to determine which channel of a plurality of channels to locate the portion of data, wherein the memory device comprises fifteen (15) channels and each page of memory in the memory array spans one of the fifteen (15) channels.