Systems for Coupling Decoders to Quantum Registers

2. The quantum computing device of claim 1, wherein each decoder block is configured to receive decoding requests from a set of n logical qubits, wherein n>1.

3. The quantum computing device of claim 1, wherein each decoder block further comprises α*l Depth First Search (DFS) engines, where 0<α<1.

4. The quantum computing device of claim 3, wherein two or more Gr-Gen modules are coupled to each DFS engine via one of a first set of multiplexers.

5. The quantum computing device of claim 4, wherein each decoder block further comprises β*l Correction (Corr) engines, where 0<β<1.

6. The quantum computing device of claim 5, wherein two or more DFS engines are coupled to each Corr engine via one of a second set of multiplexers.

7. The quantum computing device of claim 5, wherein memory requests generated by each Corr engine are routed to memory locations via one or more demultiplexers.

8. The quantum computing device of claim 5, wherein return signals are routed through each multiplexer of the first and second sets of multiplexers based on round-robin arbitration.

10. The method of claim 9, wherein each decoder block is configured to receive decoding requests from a set of n logical qubits, wherein n>1.

11. The method of claim 9, wherein each Gr-Gen module is configured to generate spanning tree memory (STM) data based on the received syndromes.

12. The method of claim 11, wherein each decoder block further comprises α*l Depth First Search (DFS) engines, where 0<α<1.

14. The method of claim 13, wherein each decoder block further comprises β*l Correction (Con) engines, where 0<β<1.