Electrical Signal Delay Calibration System

2. The electrical signal delay calibration system of claim 1, wherein the processor determines one or more combinations of signal lane pairs among the plurality of signal lanes, and determines the lane asymmetries based on a pair asymmetry of each of the signal lane pairs.

3. The electrical signal delay calibration system of claim 2, wherein each of the signal lane pairs is established by connecting the DUT receive path that is in signal communication with a first signal lane among the plurality of signal lanes with the DUT transmit path that is in signal communication with a second signal lane among the plurality of signal lanes, and connecting the DUT transmit path that is in signal communication with the first signal lane among the plurality of signal lanes with the DUT receive path that is in signal communication with the second signal lane among the plurality of signal lanes.

4. The electrical signal delay calibration system of claim 3 further comprising a plurality of pulse sensors in signal communication with the processor, each of the pulse sensors coupled to the receive signal path and the transmit signal path of a respective signal lane, wherein each of the pulse sensors assigns the transmit pulse timestamp to the transmit signal transmitted from the transmit signal path and received via the receive signal path, and assigns the receive pulse timestamp to the receive signal that is output to the transmit signal path following a predetermined time period after receiving the transmit signal and that is received via the receive signal.

5. The electrical signal delay calibration system of claim 4, wherein the processor determines the pair asymmetry for each of the signal lane pairs based on a difference between a first delay when transmitting the transmit signal from the first signal lane included in the signal lane pair to the second signal lane include in the signal lane pair and a second delay when transmitting from the second signal from the second signal lane included in the signal lane pair to the first signal lane included in the signal lane pair.

7. The electrical signal delay calibration system of claim 6, wherein the processor determines the lane asymmetry for each of the signal lanes based on a difference between the first delay and the second delay.

8. The electrical signal delay calibration system of claim 7, wherein the processor generates an optimization algorithm indicative of a signal delay in each of the signal lanes based on each of the lane asymmetries, and converges the optimization algorithm to identify each of the lane asymmetries causing the signal delay in each of the signal lanes.

9. The electrical signal delay calibration system of claim 8, wherein the processor removes each of the lane asymmetries identified by the optimization algorithm thereby minimizing the signal delay in each of the signal lanes.

10. The electrical signal delay calibration system of claim 9, wherein the processor utilizes a non-linear programming solver to converge the optimization algorithm.

15. The method of claim 14, determining, by the processor, the pair asymmetry for each of the signal lane pairs based on a difference between a first delay when transmitting the transmit signal from the first signal lane included in the signal lane pair to the second signal lane include in the signal lane pair and a second delay when transmitting from the second signal from the second signal lane included in the signal lane pair to the first signal lane included in the signal lane pair.

17. The method of claim 16, further comprising determining, by the processor, the lane asymmetry for each of the signal lanes based on a difference between the first delay and the second delay.

19. The method of claim 18, further comprising minimizing the signal delay in each of the signal lanes in response to removing, by the processor, each of the lane asymmetries identified by the optimization algorithm.

20. The method of claim 19, wherein identifying each of the lane asymmetries includes utilizing, by the processor, a nonlinear programming solver to converge the optimization algorithm.