Page Buffer Enhancements

2. The memory storage system of claim 1, wherein the second plurality of buffers are configured to encode data from the first plurality of buffers for storage in the memory array.

5. The memory storage system of claim 1, wherein the memory array comprises memory cells that each store at least one bit per cell.

6. The memory storage system of claim 5, wherein the memory array comprises single-level memory cells (SLCs), pseudo single-level memory cells (pSLC), multi-level memory cells (MLCs), triple-level memory cells (TLCs), quad-level memory cells (QLCs) or variable-level memory cells (VLCs).

7. The memory storage system of claim 1, wherein the non-volatile semiconductor memory device is a CMOS under Array (CuA) NAND semiconductor memory.

8. The memory storage system of claim 1, wherein the controller comprises a system-on-chip (SoC) controller.

9. The memory storage system of claim 1, wherein the first and second pluralities of buffers are implemented as page buffers in the nonvolatile semiconductor memory device and incorporated together with the memory array in the nonvolatile semiconductor memory device.

11. The method of claim 10, wherein the second plurality of buffers are configured to encode data from the first plurality of buffers for storage in the memory array.

14. The method of claim 10, wherein the memory array comprises memory cells that each store at least one bit per cell.

15. The method of claim 14, wherein the memory array comprises single-level memory cells (SLCs), pseudo single-level memory cells (pSLC), multi-level memory cells (MLCs), triple-level memory cells (TLCs), quad-level memory cells (QLCs) or variable-level memory cells (VLCs).

16. The method of claim 10, wherein the non-volatile semiconductor memory device is a CMOS under Array (CuA) NAND semiconductor memory.

17. The method of claim 10, wherein the controller comprises a system-on-chip (SoC) controller.

18. The method of claim 10, wherein the first and second pluralities of buffers are implemented as page buffers in the nonvolatile semiconductor memory device and incorporated together with the memory array in the nonvolatile semiconductor memory device.