Low-Power Source-Synchronous Signaling

2. The method of claim 1, wherein the comparison between the second timing signal and the distributed version of the interpolated timing signal produces phase information representing a phase difference between the second timing signal and the distributed version of the interpolated timing signal.

3. The method of claim 1, wherein the a second timing signal is phase-mixed, by the memory device, using phase mixing circuitry.

4. The method of claim 1, wherein the first timing signal and the second timing signal have a 90 degree phase relationship.

5. The method of claim 1, wherein the first timing signal and the second timing signal have a 45 degree phase relationship.

6. The method of claim 3, wherein the interpolated timing signal may be adjusted to fall over a 360 degree range when phase compared to the first timing signal.

7. The method of claim 3, wherein the phase mixing circuitry receives a complement signal of the first timing signal and a complement signal of the second timing signal.

9. The memory controller of claim 8, wherein the comparison between the second timing signal and the distributed version of the interpolated timing signal produces phase information representing a phase difference between the second timing signal and the distributed version of the interpolated timing signal.

10. The memory controller of claim 8, wherein the second timing signal is phase-mixed, by the memory device, with the first timing signal using phase mixing circuitry.

11. The memory controller of claim 8, wherein second timing signal generating circuitry is to generate the second timing signal to have a 90 degree phase relationship with the first timing signal.

12. The memory controller of claim 8, wherein second timing signal generating circuitry is to generate the second timing signal to have a 45 degree phase relationship with the first timing signal.

13. The memory controller of claim 10, wherein the interpolated timing signal may be adjusted to fall over a 360 degree range when phase compared to the first timing signal.

14. The memory controller of claim 13, wherein the phase mixing circuitry is to receive a complement signal of the first timing signal and a complement signal of the second timing signal.

15. The memory controller of claim 8, wherein the memory device is a dynamic random access memory (DRAM) device.

17. The memory controller of claim 16, wherein the comparison between the quadrature timing signal and the distributed version of the interpolated timing signal produces phase information representing a phase difference between the quadrature timing signal and the distributed version of the interpolated timing signal.

18. The memory controller of claim 16, wherein the quadrature timing signal is phase-mixed with the in-phase timing signal using phase mixing circuitry.

19. The memory controller of claim 18, wherein the interpolated timing signal may be adjusted, by the phase mixing circuitry, to fall over a 360 degree range when phase compared to the in-phase timing signal.

20. The memory controller of claim 19, wherein the phase mixing circuitry is to receive a complement signal of the quadrature timing signal and a complement signal of the in-phase timing signal.