Off-Module Data Buffer

2. The data buffer IC of claim 1 wherein the programmable register comprises circuitry to store, as the configuration information, a multi-bit value that indicates (i) whether or not the first memory-module socket is populated with a memory module, and (ii) whether or not the second memory-module socket is populated with a memory module.

4. The data buffer IC of claim 1 wherein, if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules, the configuration information additionally indicates whether (i) a single one of the respective memory modules is to be accessed exclusively per memory access transaction, or (ii) both of the respective memory modules are to be accessed per memory access transaction.

5. The data buffer IC of claim 4 wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to (i) enable oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enable oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.

6. The data buffer IC of claim 5 wherein the primary data interface comprises a synchronous signaling interface timed by a primary-interface timing signal that oscillates at the first frequency.

7. The data buffer IC of claim 1 wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to disable distribution of the one or more timing signal instances within one of the first and second secondary data interfaces in response to configuration information, stored within the programmable register, that indicates that only one of the first and second memory-module sockets is populated with a memory module.

8. The data buffer IC of claim 1 further comprising a first control interface to receive control signals from a first registered clock driver chip that is distinct from the memory control component.

9. The data buffer IC of claim 8 wherein the first control interface comprises one or more signaling contacts to receive the control signals from the first registered clock driver chip via one or more counterpart signaling contacts within the first memory-module socket, and wherein the data buffer IC further comprises a second control interface having one or more signaling contacts to receive control signals from a second registered clock driver chip via one or more counterpart signaling contacts within the second memory-module socket.

10. The data buffer IC of claim 8 wherein the first control interface to receive control signals from the first registered clock driver chip comprises circuitry to receive, via the control signals, the configuration information and a command to store the configuration information within the programmable register.

12. The method of claim 11 wherein storing the configuration information within the programmable register comprises storing a multi-bit value that indicates (i) whether or not the first memory-module socket is populated with a memory module, and (ii) whether or not the second memory-module socket is populated with a memory module.

14. The method of claim 11 wherein, if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules, the configuration information additionally indicates whether (i) a single one of the respective memory modules is to be accessed exclusively per memory access transaction, or (ii) both of the respective memory modules are to be accessed per memory access transaction.

15. The method of claim 14 wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising (i) enabling oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enabling oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.

16. The method of claim 11 wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising disabling distribution of the one or more timing signal instances within one of the first and second secondary data interfaces in response to configuration information, stored within the programmable register, that indicates that only one of the first and second memory-module sockets is populated with a memory module.

17. The method of claim 11 further comprising receiving, via a first control interface of the data buffer IC, control signals from a first registered clock driver chip that is distinct from the memory control component.

18. The method of claim 17 wherein receiving the control signals from the first registered clock driver chip comprises receiving first control signals output from the first registered clock driver chip to the first control interface via one or more signaling contacts within the first memory-module socket, the method further comprising receiving second control signals output from a second registered clock driver chip to a second control interface of the data buffer IC via one or more signaling contacts within the second memory-module socket.

19. The method of claim 17 wherein receiving the control signals from the first registered clock driver chip comprises receiving the configuration information and a command to store the configuration information within the programmable register.