Integrated Circuit Side-Channel Mitigation Mechanism

2. The apparatus of claim 1, wherein the jammer circuitry masks signals generated by processing of secure data by the cryptographic algorithms.

3. The apparatus of claim 2, wherein the jammer circuitry masks the signals by decreasing a signal-to-noise ratio of the signals by adding the noise generated at a CFU.

4. The apparatus of claim 3, wherein each of the plurality of CFUs perform a different cryptographic algorithm.

5. The apparatus of claim 1, wherein the jammer circuitry further comprises a state decoder to receive the integer values from the random number generator and convert the integer values into a bit vector.

6. The apparatus of claim 5, wherein a value of the bit vector is determined by the first integer value and the second integer value.

7. The apparatus of claim 6, wherein the plurality of flip-flops store the bit vector.

8. The apparatus of claim 7, wherein gated output states and the switching of the states of the plurality of flip-flops generates the noise.

9. The apparatus of claim 2, wherein the cryptographic circuitry further comprises control circuitry to receive control signals to enable and disable the jammer circuitry.

12. The method of claim 11, wherein generating the noise masks processing of secure data by the cryptographic algorithms.

15. The security engine of claim 14, wherein a value of the bit vector is determined by the first integer value and the second integer value.

16. The security engine of claim 15, wherein the plurality of flip-flops store the bit vector.

17. The security engine of claim 16, wherein gated output states and the switching of the states of the plurality of flip-flops generates the noise.

18. The security engine of claim 13, wherein the cryptographic circuitry further comprises control circuitry to receive control signals from the micro-controller to enable and disable the jammer circuitry.