Fuse Latch of Semiconductor Device for Latching Data of a Repair Fuse Cell

1. A fuse latch of a semiconductor device comprising: first and second NMOS transistors, each of which receives a first control signal through a gate terminal and transmits fuse cell data in response to the first control signal; a first inverter configured to include a first PMOS transistor and a third NMOS transistor coupled in series between a power supply voltage terminal and a ground voltage terminal, with an input node of the first inverter coupled to the second NMOS transistor and an output node of the first inverter coupled to the first NMOS transistor; a second inverter configured to include a second PMOS transistor and a fourth NMOS transistor coupled in series between the power supply voltage terminal and the ground voltage terminal, with an input node of the second inverter coupled to the output node of the first inverter and an output node of the second inverter coupled to the input node of the first inverter; a fifth NMOS transistor, with a gate terminal coupled to the input node of the first inverter and the output node of the second inverter and with a first terminal coupled to a data output terminal; and a sixth NMOS transistor configured to receive a second control signal through a gate terminal and to selectively couple the ground voltage terminal to a second terminal of the fifth NMOS transistor in response to the second control signal, wherein a portion of the second NMOS transistor and a portion of the fourth NMOS transistor are included in a first active region; a portion of the second PMOS transistor is included in a second active region; a portion of the first PMOS transistor is included in a third active region; a portion of the first NMOS transistor and a portion of the third NMOS transistor are included in a fourth active region; a portion of the fifth NMOS transistor and a portion of the sixth NMOS transistor are included in a fifth active region; and the first active region, the second active region, the third active region, the fourth active region, and the fifth active region are sequentially arranged in a first direction.

2. The fuse latch of the semiconductor device according to claim 1, wherein: the fourth and second NMOS transistors are spaced apart in a second direction perpendicular to the first direction and portions of each are respectively disposed at both ends of the first active region.

3. The fuse latch of the semiconductor device according to claim 1, wherein: the portion of the second PMOS transistor is disposed at one end of the second active region, which extends in a second direction perpendicular to the first direction.

4. The fuse latch of the semiconductor device according to claim 1, wherein: the portion of the first PMOS transistor is disposed at one end of the third active region, which extends in a second direction perpendicular to the first direction.

5. The fuse latch of the semiconductor device according to claim 1, wherein: the third and first NMOS transistors are spaced apart in a second direction perpendicular to the first direction and portions of each are respectively disposed at both ends of the fourth active region.

6. The fuse latch of the semiconductor device according to claim 1, wherein: the fifth and sixth NMOS transistors are spaced apart in a second direction perpendicular to the first direction and portions of each are respectively disposed at both ends of the fifth active region.

7. The fuse latch of the semiconductor device according to claim 1, wherein: each of the first through fifth active regions extend in a second direction perpendicular to the first direction, and a length of the second active region and a length of the third active region are each less than a length of the first, fourth or fifth active regions.

8. The fuse latch of the semiconductor device according to claim 1, further comprising: a first line disposed at an end of the fourth active region in a second direction perpendicular to the first direction and configured to supply the fuse cell data; a second line disposed at an end of the first active region in the second direction and configured to supply the fuse cell data; a first power-supply line disposed at an other end of the second and third active regions, spaced apart in the second direction from the ends of the first and fourth active regions, and configured to supply a power supply voltage; a second power-supply line disposed at an other end, in the second direction, of the first active region and configured to supply a ground voltage; a third power-supply line disposed at an other end, in the second direction, of the fourth active region and configured to supply the ground voltage; and a fourth power-supply line disposed at an end of the fifth active region, spaced apart in the second direction from the ends of the first and fourth active regions, and configured to supply the ground voltage.

9. The fuse latch of the semiconductor device according to claim 8, wherein: the second and third active regions are disposed, in the first direction, between the first active region and the fourth active region; and the first line and the second line are spaced apart in the first direction from each other by a distance between the first active region and the fourth active region.

10. The fuse latch of the semiconductor device according to claim 1, wherein: the first to fifth active regions are sequentially arranged in an N-P-P-N-N structure in the first direction.

11. The fuse latch of the semiconductor device according to claim 1, wherein: the transistors in the first, fourth, and fifth active regions are arranged in two columns that extend in the first direction.

12. The fuse latch of the semiconductor device according to claim 1, wherein: the transistors of each of the second and third active regions are arranged in one column that extend in the first direction.

13. The fuse latch of the semiconductor device according to claim 1, further comprising: a first pickup guard ring region disposed at an uppermost outer wall in the first direction and configured to pick up an adjacent well of the first active region; and a second pickup guard ring region disposed at a lowermost outer wall in the first direction, and configured to pick up an adjacent well of the fifth active region.

14. The fuse latch of the semiconductor device according to claim 13, further comprising: a third pickup guard ring region configured to pick up an adjacent well of the fourth active region farthest from the second pickup guard ring region in the first direction.

15. The fuse latch of the semiconductor device according to claim 1, wherein: each portion of the PMOS transistors and the NMOS transistors includes a source region and a drain region.