Power Efficient Circuits and Methods for Phase Alignment

1. A clock-generation circuit comprising: a phase interpolator to issue a phase-interpolated clock signal of a phase-interpolated clock period; and a fractional-delay circuit coupled to the phase interpolator to receive the phase-interpolated clock signal, the fractional-delay circuit including: a first fractional delay element having a first control node to receive a first delay-control signal, a first input node to receive a reference clock signal, and a first output node to issue a first fractional-delay clock signal phase offset from the reference clock signal by a first delay that is a function of the first delay-control signal and is a first fraction of the phase-interpolated clock period; and a second fractional delay element having a second control node to receive a second delay-control signal, a second input node to receive the reference clock signal, and a second output node to issue a second fractional-delay clock signal phase offset from the reference clock signal by a second delay that is a function of the second delay-control signal and is a second fraction of the phase-interpolated clock period.

2. The circuit of claim 1, wherein the phase interpolator issues the phase-interpolated clock signal responsive to the reference clock signal.

3. The circuit of claim 1, wherein each of the first fractional delay element and the second fractional delay element is passive.

4. The circuit of claim 3, wherein the passive first and second fractional delay elements exhibit respective first and second RC time constants that are the respective functions of the first and second delay-control signals.

5. The circuit of claim 1, further comprising a state machine coupled to the control node of each of the first and second fractional delay elements, the state machine to generate a digital value for the first and second delay-control signals.

6. The circuit of claim 1, further comprising a second delay element coupled in series with each of the first and second fractional delay elements.

7. The circuit of claim 1, wherein the first and second fractions of the phase-interpolated clock period are less than one.

8. The circuit of claim 1, wherein each of the first and second fractions of the phase-interpolated clock period is an integer multiple of the phase-interpolated clock period divided by a power of two.

9. The circuit of claim 8, wherein the power of two is sixty-four.

10. An integrated-circuit (IC) module comprising: a printed-circuit board having signal traces; and IC components interconnected via the signal traces, at least one of the IC components including: a phase interpolator to issue an interpolated clock signal of a phase-interpolated clock period; and a fractional-delay circuit coupled to the phase interpolator to receive the phase-interpolated clock signal, the fractional-delay circuit including: a first fractional delay element having a first control node to receive a first delay-control signal, a first input node to receive a reference clock signal, and a first output node to issue a first fractional-delay clock signal phase offset from a reference clock signal by a first delay that is a first fraction of the phase-interpolated clock period and a function of the first delay-control signal; and a second fractional delay element having a second control node to receive a second delay-control signal, a second input node to receive the reference clock signal, and a second output node to issue a second fractional-delay clock signal phase offset from the reference clock signal by a second delay that is a second fraction of the phase-interpolated clock period and a function of the second delay-control signal.

11. The module of claim 10, wherein the phase interpolator issues the interpolated clock signal responsive to the reference clock signal.

12. The module of claim 10, wherein each fractional delay element is passive.

13. The module of claim 12, wherein each of the first and second fractional delay elements exhibits a respective RC time constant that is the function of the respective one of the first and second delay-control signals.

14. The module of claim 10, the at least one of the IC components comprising a state machine coupled to the control node of each of the first and second fractional delay elements, the state machine to generate a digital value for each of the first and second delay-control signals.

15. The module of claim 10, wherein the IC components include memory components, and wherein the at least one of the IC components buffers data signals to at least one of the memory components.

16. A method comprising: interpolating between phases of a reference clock signal to produce an interpolated clock signal phase shifted with respect to the reference clock signal; delaying the reference clock signal by N+1 phase delays, where N is at least one, to produce N+1 delayed clock signals independently phase shifted with respect to the reference clock signal; and phase aligning each of the N+1 delayed clock signals with the interpolated clock signal.

17. The method of claim 16, further comprising ceasing the interpolating after the phase aligning and maintaining the phase aligning absent the interpolating.

18. The method of claim 16, further comprising gating N+1 data signals each responsive to a respective one of the N+1 delayed clock signals.

19. The method of claim 18, further comprising passing the N+1 data signals to a memory component.

20. The method of claim 16, wherein the interpolating comprises drawing power from a power supply and the delaying comprises passively conveying the reference clock signal absent the power supply.