Multicore, Multibank, Fully Concurrent Coherence Controller

1. A system comprising: a cache tag bank; a snoop filter bank coupled to the cache tag bank; a memory bank coupled to the cache tag bank; and a controller coupled to the cache tag bank, the controller configured to: receive a first read request that includes a first address tag; apply the first address tag to the snoop filter bank to determine that a unique state is associated with the first address tag; issue a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag; if the first snoop request returns a first value, respond to the first read request with the first value; and if the first snoop request does not return a value, retrieve a second value from the memory bank or from an external memory and respond to the first read request with the second value.

2. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag; determine that a third value associated with the second address tag is stored in the memory bank; and determine a snoop state associated with the second address tag.

3. The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating an invalid state: retrieve the third value from the memory bank; and respond to the second read request with the third value.

4. The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating a shared state: retrieve the third value from the memory bank; and respond to the second read request with the third value.

5. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a third value associated with the second address tag is stored in the memory bank; and determine a snoop state associated with the second address tag.

6. The system of claim 5, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state: issue a second snoop request to a processor associated with the second address tag to invalidate the third value stored by the processor; and write a fourth value associated with the second address tag to the memory bank.

7. The system of claim 5, wherein: in response to the snoop state indicating an invalid state, the controller is configured to write a fourth value associated with the second address tag to the memory bank.

8. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag; and determine that a value associated with the second address tag is not stored in the memory bank; and determine a snoop state associated with the second address tag.

9. The system of claim 8, wherein: in response to the snoop state indicating the unique state or a shared state, the controller is configured to issue a second snoop request to a processor associated with the second address tag; in response to the second snoop request returning a third value, the controller is configured to respond to the second read request with the third value; and in response to the second snoop request not returning a value, the controller is configured to: retrieve a fourth value from the external memory; and respond to the second read request with the fourth value.

10. The system of claim 8, wherein the controller is configured to, in response to the snoop state indicating an invalid state: retrieve a third value from the external memory; and respond to the second read request with the third value.

11. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a value associated with the second address tag is not stored in the memory bank; and determine a snoop state associated with the second address tag.

12. The system of claim 11, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state: issue a second snoop request to a processor associated with the second address tag to invalidate a third first value stored by the processor; and write a fourth value associated with the second address tag to the external memory.

13. The system of claim 11, wherein: in response to the snoop state indicating an invalid state, the controller is configured to write a third value associated with the second address tag to the external memory.

14. A method comprising: receiving, at a controller, a read request that includes a first address tag; applying, by the controller, the first address tag to a plurality of snoop filter banks coupled to a plurality of cache tag banks to determine that a unique state is associated with the first address tag; issuing, by the controller, a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag; if the first snoop request returns a first value, responding, by the controller, to the read request with the first value; and if the first snoop request does not return a value, retrieving, by the controller, a second value from a plurality of memory banks coupled to the plurality of cache tag banks or from an external memory and respond to the read request with the second value, wherein: each of the plurality of cache tag banks, the plurality of snoop filter banks, and the plurality of memory banks is coupled by respective cache way lines; and the controller is configured to access each line of the respective cache way lines in parallel.

15. The method of claim 14, wherein: the plurality of cache tag banks includes a common cache tag bank; and the plurality of snoop filter banks and the plurality of memory banks share the common cache tag bank.

16. The system of claim 1, wherein the cache tag bank is configured to be shared by the snoop filter bank and the memory bank.

17. The system of claim 1, wherein: the cache tag bank is a common cache tag bank; and the snoop filter bank and the memory bank share the common cache tag bank.

18. The system of claim 1, wherein the controller is configured to: determine that the snoop filter bank stores an identifier of the peripheral, wherein the identifier is associated with the first address tag; and determine that the snoop filter bank indicates that data associated with the first address tag is stored in a cache of the peripheral.

19. The system of claim 2, wherein the controller is configured to determine that the third value is stored in the memory bank by at least applying the first address tag to the cache tag bank.

20. The system of claim 4, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.