Memory Interface Having Multiple Snoop Processors

1. A method for interfacing, at a memory interface, between a memory bus and a cache memory comprising a plurality of cache banks, the memory interface comprising a plurality of snoop processors configured to receive snoop requests from the memory bus, each snoop processor being associated with a respective bus interface, and each bus interface being configured to transfer data to one or more cache banks, of the plurality of cache banks, associated with that bus interface, the method comprising: receiving a snoop request at a respective bus interface associated with the snoop processor; determining, at the snoop processor, that the snoop request relates to said respective bus interface; and processing the snoop request at a cache bank associated with said respective bus interface in dependence on that determination.

2. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a memory interface for interfacing between a memory bus and a cache memory comprising a plurality of cache banks, the memory interface comprising a plurality of snoop processors configured to receive snoop requests from the memory bus, wherein each snoop processor is associated with a respective bus interface, each bus interface configured to transfer data to one or more cache banks, of the plurality of cache banks, associated with that bus interface, wherein the memory interface is configured to process a snoop request at a cache bank associated with a respective bus interface in response to a snoop processor determining that the snoop request, received from the respective bus interface associated with said snoop processor, relates to the said respective bus interface.

3. A memory interface for interfacing between a memory bus and a cache memory comprising a plurality of cache banks, the memory interface comprising a plurality of snoop processors configured to receive snoop requests from the memory bus, wherein each snoop processor is associated with a respective bus interface, each bus interface configured to transfer data to one or more cache banks, of the plurality of cache banks, associated with that bus interface, wherein the memory interface is configured to process a snoop request at a cache bank associated with a respective bus interface in response to a snoop processor determining that the snoop request, received from the respective bus interface associated with said snoop processor, relates to said respective bus interface.

4. The memory interface according to claim 3, in which the memory interface comprises a data structure configured to maintain a mapping between each of the plurality of bus interfaces and respective sets of memory addresses.

5. The memory interface according to claim 3, in which each snoop processor is configured to map the memory addressed by the snoop request to a cache bank of the plurality of cache banks in a first mapping, and to map the cache bank to one of the plurality of bus interfaces in a second mapping.

6. The memory interface according to claim 5, in which each snoop processor is configured to perform at least one of the first mapping and the second mapping by using a hash function.

7. The memory interface according to claim 3, in which the memory interface is configured to determine that the snoop request relates to said respective bus interface in dependence on determining that the cache bank associated with said respective bus interface is associated with the memory addressed by the snoop request.

8. The memory interface according to claim 3, in which the memory addressed by the snoop request is a physical address in a physical address space.

9. The memory interface according to claim 3, comprising a cache line status data structure configured to store status information relating to cache lines at the cache memory, each snoop processor being configured to generate a response to the snoop request in dependence on status information stored in the cache line status data structure if the snoop request relates to the bus interface associated with that snoop processor.

10. The memory interface according to claim 3, in which each snoop processor comprises a bus calculation module for calculating the bus interface to which the snoop request relates.

11. The memory interface according to claim 10, in which the memory interface comprises a data structure configured to maintain a mapping between each of the plurality of bus interfaces and respective sets of memory addresses, and the bus calculation module is configured to calculate the bus interface to which the snoop request relates in dependence on the mapping maintained at the data structure.

12. The memory interface according to claim 10, in which each snoop processor is configured to map the memory addressed by the snoop request to a cache bank of the plurality of cache banks in a first mapping, and to map the cache bank to one of the plurality of bus interfaces in a second mapping, and the bus calculation module is configured to perform at least one of the first mapping and the second mapping.

13. The memory interface according to claim 3, in which each snoop processor comprises a buffer for storing received snoop requests.

14. The memory interface according to claim 13, in which each snoop processor is configured to process snoop requests on the buffer in a different order to that in which the snoop requests were received.

15. The memory interface according to claim 8, in which the cache memory uses a virtual address space, the memory interface comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space, the reverse translation module being configured to translate the snoop request to a translated snoop request addressed in the virtual address space.

16. The memory interface according to claim 15, in which the reverse translation module comprises a reverse translation data structure configured to maintain a mapping from the physical address space to the virtual address space.

17. The memory interface according to claim 16, in which the reverse translation data structure comprises a directory linking a physical address in the physical address space to a corresponding virtual address in the virtual address space.

18. The memory interface according to claim 15, in which the memory interface is configured to determine the cache bank to which the translated snoop request is addressed in dependence on the reverse translation module.

19. The memory interface according to claim 16, in which the reverse translation data structure is configured to map the memory addressed by the snoop request to a cache bank of the plurality of cache banks in a first mapping, and to map the cache bank to one of the plurality of bus interfaces in a second mapping.

20. The memory interface according to claim 3, wherein the memory interface is embodied in hardware on an integrated circuit.