Device of Generating Reference Voltages for Multi-Level Signaling and Memory System Including the Same

1. A reference voltage generation device comprising: a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme; and a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, the second electronic device configured to use the three or more reference voltages, wherein the noise information generation circuit includes a power noise transmitter electrically connected with the first power, the second power and a first terminal, and configured to output the first power noise and the second power noise to the first terminal.

2. The reference voltage generation device of claim 1, wherein the noise information generation circuit includes: a power noise receiver included in the second electronic device, the power noise receiver configured to receive the first and second power noises through a second terminal, the second terminal connected with the first terminal through the communication line.

3. The reference voltage generation device of claim 2, wherein the power noise receiver is electrically connected with the first power and the second terminal.

4. The reference voltage generation device of claim 2, wherein the power noise transmitter includes a first resistor and a second resistor connected in series between the first power and the second power, and the power noise receiver includes a third resistor electrically connected between the first power and the second terminal.

5. The reference voltage generation device of claim 4, wherein the first terminal is connected with a first node, and the first node is between the first resistor and the second resistor.

6. The reference voltage generation device of claim 4, wherein, when the first resistor has a first resistance value and the second resistor has a second resistance value, the power noise receiver is configured to output a first noise signal, wherein, when each of the first resistor and the second resistor has a third resistance value, the power noise receiver is configured to output a second noise signal, and wherein, when the first resistor has the second resistance value and the second resistor has the first resistance value, the power noise receiver is configured to output a third noise signal.

7. The reference voltage generation device of claim 6, wherein the power noise information includes the first noise signal, the second noise signal, and the third noise signal.

8. The reference voltage generation device of claim 6, wherein the reference voltage generation circuit includes: a voltage generator configured to output a first voltage, a second voltage, and a third voltage; a first adder configured to output a value obtained by adding the first voltage and the first noise signal as a first reference voltage; a second adder configured to output a value obtained by adding the second voltage and the second noise signal as a second reference voltage; and a third adder configured to output a value obtained by adding the third voltage and the third noise signal as a third reference voltage.

9. The reference voltage generation device of claim 6, wherein the reference voltage generation circuit includes: a voltage generator configured to output a first voltage, a second voltage, and a third voltage; a first adder configured to output a value obtained by adding the first voltage and the first noise signal as a first reference voltage; a second adder configured to output a value obtained by adding the first noise signal and the third noise signal; a first multiplier configured to output a value obtained by multiplying a ratio and a value output from the second adder; a third adder configured to output a value obtained by adding the second voltage and a value output from the first multiplier as a second reference voltage; and a fourth adder configured to output a value obtained by adding the third voltage and the third noise signal as a third reference voltage.

10. The reference voltage generation device of claim 1, wherein the multi-level signaling scheme is a pulse amplitude modulation level-4 (PAM4) scheme.

11. A memory system comprising: a memory controller; and a memory device connected with the memory controller through a plurality of channels, wherein the memory device includes local reference voltage generation circuits corresponding to the plurality of channels, and wherein each of the local reference voltage generation circuits is configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to the memory controller and propagated from the memory controller to the memory device through a communication line; and generate three or more reference voltages for multi-level signaling based on the power noise information, wherein the multi-level signaling includes a pulse amplitude modulation level-4 (PAM4) scheme.

12. The memory system of claim 11, wherein the plurality of channels include a first channel and a second channel, the local reference voltage generation circuits include a first local reference voltage generation circuit and a second local reference voltage generation circuit, and the first local reference voltage generation circuit is configured to receive first power noise information from a first noise information generation circuit corresponding to the first channel, and receive second power noise information from a second noise information generation circuit corresponding to the first channel, and the second local reference voltage generation circuit is configured to receive third power noise information from a third noise information generation circuit corresponding to the second channel, and receive fourth power noise information from a fourth noise information generation circuit corresponding to the second channel.

13. The memory system of claim 12, wherein the first power noise information and the third power noise information are identical to each other, and the second power noise information and the fourth power noise information are identical to each other.

14. The memory system of claim 13, wherein the first power noise information and the third power noise information correspond to a first signal level of the multi-level signaling, and the second power noise information and the fourth power noise information correspond to a second signal level of the multi-level signaling.

15. The memory system of claim 12, wherein the first noise information generation circuit includes a first resistor and a second resistor connected sequentially in series between the first power and the second power supplied to the memory controller, the second noise information generation circuit includes a third resistor and a fourth resistor connected sequentially in series between the first power and the second power supplied to the memory controller, the third noise information generation circuit includes a fifth resistor and a sixth resistor connected sequentially in series between the first power and the second power supplied to the memory controller, wherein the fourth noise information generation circuit includes a seventh resistor and an eighth resistor connected sequentially in series between the first power and the second power supplied to the memory controller, resistance values of the first resistor, the fourth resistor, the fifth resistor, and the eighth resistor are identical to each other, and resistance values of the second resistor, the third resistor, the sixth resistor, and the seventh resistor are identical to each other.

16. The memory system of claim 11, wherein the plurality of channels include a first channel and a second channel, the local reference voltage generation circuits include a first local reference voltage generation circuit and a second local reference voltage generation circuit, the first local reference voltage generation circuit is configured to receive first power noise information from a first noise information generation circuit corresponding to the first channel, and receive second power noise information from a second noise information generation circuit corresponding to the first channel, and the second local reference voltage generation circuit is configured to receive the second power noise information from the second noise information generation circuit corresponding to the second channel, and receive the first power noise information from the first noise information generation circuit corresponding to the first channel.

17. The memory system of claim 16, wherein the first power noise information and the second power noise information are different from each other.

18. The memory system of claim 17, wherein the first power noise information corresponds to a first signal level of the multi-level signaling, and the second power noise information corresponds to a second signal level of the multi-level signaling.

19. The memory system of claim 16, wherein the first noise information generation circuit includes a first resistor and a second resistor connected sequentially in series between the first power and the second power supplied to the memory controller, the second noise information generation circuit includes a third resistor and a fourth resistor connected sequentially in series between the first power and the second power supplied to the memory controller, resistance values of the first resistor and the fourth resistor are identical to each other, and resistance values of the second resistor and the third resistor are identical to each other.

20. A reference voltage generation device comprising: a noise information generation circuit including a power noise transmitter and a power noise receiver, the power noise transmitter included in a first electronic device, and the power noise receiver included in a second electronic device; and a reference voltage generation circuit configured to generate three or more reference voltages used in the second electronic device, the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme, wherein the noise information generation circuit is configured to generate power noise information based on a first power noise and a second power noise, and the first power noise and the second power noise are generated based on a first power and a second power supplied to the first electronic device and propagated from the first electronic device to the second electronic device through a communication line, the reference voltage generation circuit is configured to generate the three or more reference voltages for the multi-level signaling scheme based on the power noise information, the power noise transmitter is configured to output the first and second power noises to a first terminal, the power noise receiver is configured to receive the first and second power noises through a second terminal, the second terminal connected with the first terminal through the communication line, and the multi-level signaling scheme is a pulse amplitude modulation level-4 (PAM4) scheme.