Receiver Circuits

1. A receiver circuit comprising: a plurality of data lane modules, each of the plurality of data lane modules configured to receive respective data signals; a clock lane module configured to receive clock signals and configured to provide each of the plurality of data lane modules with a respective divided clock signal among divided clock signals based on the clock signals; a bias current controller configured to control a clock bias current provided to the clock lane module; and a link layer configured to provide a bias control signal to the bias current controller and configured to provide clock gating signals to the clock lane module based on levels of low power data signals output from the plurality of data lane modules and low power clock signals output from the clock lane module, and wherein the bias current controller, based on the bias control signal, is configured to cut off the clock bias current in a first power mode, provide the clock bias current having a first magnitude to the clock lane module in a second power mode, and provide the clock bias current having a second magnitude greater than the first magnitude to the clock lane module in a third power mode.

2. The receiver circuit of claim 1, wherein the link layer is configured to determine a power mode of the clock lane module and the plurality of data lane modules as one of the first power mode, the second power mode and the third power mode based on the levels of the low power data signals and the low power clock signals, and wherein the clock lane module is configured to, in the second power mode, generate the divided clock signals provided to the plurality of data lane modules based on the clock gating signals.

3. The receiver circuit of claim 2, wherein: in the first power mode, the clock lane module and the plurality of data lane modules operate in a low power mode; in the second power mode, the clock lane module operates in a high speed mode and the plurality of data lane modules operate in the low power mode; and in the third power mode, the clock lane module and the plurality of data lane modules operate in the high speed mode.

4. The receiver circuit of claim 3, wherein: in the low power mode, the received clock signals swing between a ground voltage and a first voltage level greater than the ground voltage; in the high speed mode, the received clock signals swings between a voltage level greater than the ground voltage and a voltage level less than the first voltage level; in the low power mode, each of the low power data signals swings between the ground voltage and a second voltage level greater than the ground voltage; and in the high speed mode, the data signals include packet data when both the clock lane module and the plurality of data lane modules operate in the high speed mode.

5. The receiver circuit of claim 1, wherein the clock lane module includes: a termination circuit connected between a first reception terminal and a second reception terminal, the termination circuit configured to receive a first clock signal of the clock signals via the first reception terminal, and the termination circuit configured to receive a second clock signal of the clock signals via the second reception terminal; a first receiver configured to receive the first clock signal and output a first low power clock signal based on the first clock signal; a second receiver configured to receive the second clock signal and output a second low power clock signal based on the second clock signal; a third receiver configured to receive the first clock signal and the second clock signal and output a high speed clock signal based on the first clock signal and the second clock signal; a reference clock generator configured to generate a reference clock signal based on the high speed clock signal and to provide the reference clock signal to the link layer; and a divided clock signal generator configured to generate the divided clock signals based on the high speed clock signal.

6. The receiver circuit of claim 5, wherein the link layer is configured to enable the termination circuit and the third receiver in both the second power mode and the third power mode, wherein the termination circuit includes; a first transistor connected to the first reception terminal; a first termination resistor connected between the first transistor and a first node; a second transistor connected to the second reception terminal; a second termination resistor connected between the second transistor and the first node; and a capacitor coupled between the first node and a ground voltage.

7. The receiver circuit of claim 6, wherein the first transistor and the second transistor are configured to be turned-on in either of the second power mode and the third power mode, in response to a first enable signal.

8. The receiver circuit of claim 5, wherein the divided clock signal generator includes a plurality of AND gates configured to perform AND operations on the high speed clock signal and the clock gating signals to output the divided clock signals, respectively.

9. The receiver circuit of claim 5, wherein the third receiver includes: a source current generation circuit connected to a power supply voltage, the source current generation circuit configured to receive the clock bias current and configured to generate at least one source current corresponding to the clock bias current; and at least two amplifying stages including a first amplifier stage configured to receive the first clock signal and the second clock signal and to amplify a difference between the first clock signal and the second clock signal based on the at least one source current, and a second amplifier stage configured to output the high speed clock signal.

10. The receiver circuit of claim 1, wherein each of the plurality of data lane modules includes: a termination circuit connected between a first reception terminal and a second reception terminal, the termination circuit configured to receive a first data signal of the data signals via the first reception terminal and receive a second data signal of the data signals via the second reception terminal; a first receiver configured to receive the first data signal and output a first low power data signal based on the first data signal; a second receiver configured to receive the second data signal and output a second low power data signal based on the second data signal; a third receiver configured to receive the first data signal and the second data signal and output a high speed data signal based on the first data signal and the second data signal; and a deserializer configured to output a parallel data signal by deserializing the high speed data signal based on the respective divided clock signal.

11. The receiver circuit of claim 1, wherein the link layer includes: a control and interface logic configured to generate a first enable signal and second enable signals based on the low power data signals and the low power clock signals, the first enable signal being for enabling a termination circuit and a high speed receiver of the clock lane module, the second enable signal being for enabling the termination circuit and the high speed receiver of each of the plurality of data lane modules; a plurality of clock gating signal generators configured to generate the clock gating signals based on the second enable signals; and a bias signal generator configured to generate the bias control signal based on the second enable signals, and wherein the bias signal generator is configured to generate the bias control signal such that, the clock bias current has the first magnitude in response to the second enable signals designating the second power mode, and the clock bias current has the second magnitude in response to the second enable signals designating the third power mode.

12. The receiver circuit of claim 11, wherein the bias signal generator includes: an AND gate configured to output a selection signal by performing an AND operation on the second enable signals; and a multiplexer configured to output one of a first bias control signal associated with the first magnitude and a second bias control signal associated with the second magnitude as the bias control signal in response to the selection signal.

13. The receiver circuit of claim 1, wherein the clock signals and the data signals are based on a mobile industry processor interface (MIPI) D-PHY protocol.

14. A receiver circuit comprising: a plurality of trio modules, each of the trio modules configured to receive three or more signals; a bias current controller configured to control a bias current provided to each of the plurality of trio modules; and a link layer configured to provide a bias control signal to the bias current controller based on levels of low power signals output from the plurality of trio modules, wherein the bias current controller, based on the bias control signal, is configured to: cut off the bias current in a first power mode; output the bias current having a first magnitude in a second power mode; and output the bias current having a second magnitude in a third power mode.

15. The receiver circuit of claim 14, wherein the link layer is configured to determine a power mode of the plurality of trio modules as one of the first power mode, the second power mode and the third power mode based on the levels of the low power signals, and in the first power mode, the plurality of trio modules operate in a low power mode; in the second power mode, a first trio module from among the plurality of trio modules operates in the low power mode and other trio modules from among the plurality of trio modules operate in a high speed mode; and in the third power mode, the plurality of trio modules operate in the high speed mode.

16. The receiver circuit of claim 15, wherein each of the plurality of trio modules includes: a termination circuit connected to a first reception terminal, a second reception terminal, and a third reception terminal, the termination circuit is configured to receive a first signal from among the three or more signals via the first reception terminal, receive a second signal from among the three or more signals via the second reception terminal, and receive a third signal from among the three or more signals via the third reception terminal; a first low power receiver configured to receive the first signal and output a first low power signal based on the first signal; a second low power receiver configured to receive the second signal and output a second low power signal based on the second signal; a third low power receiver configured to receive the third signal and output a third low power signal based on the third signal; a first high speed receiver configured to receive the first signal and the second signal and output a first high speed signal by amplifying a difference between the first signal and the second signal; a second high speed receiver configured to receive the second signal and the third signal and output a second high speed signal by amplifying a difference between the second signal and the third signal; a third high speed receiver configured to receive the third signal and the first signal and output a third high speed signal by amplifying a difference between the third signal and the first signal; a clock and data recovery circuit configured to recover a data signal and a data clock signal based on the first high speed signal, the second high speed signal and the third high speed signal; and a reference clock generator configured to generate a reference clock signal based on the first high speed signal, the second high speed signal and the third high speed signal.

17. The receiver circuit of claim 16, wherein the link layer is configured to: in the second power mode, enable the first through third high speed receivers and the termination circuit of the first trio module and disable the first through third high speed receivers and the termination circuit of each of the remaining trio modules; and in the third power mode, enable the first through third high speed receivers and the termination circuit of each of the plurality of trio modules.

18. The receiver circuit of claim 14, wherein the link layer includes: a control and interface logic generate enable signals for enabling a termination circuit and high speed receivers of each of the plurality of trio modules based on the levels of the low power signals; and a bias signal generator configured to generate the bias control signal based on the enable signals, and the bias signal generator is configured to generate the bias control signal such that: the bias current has the first magnitude in response to the enable signals designating the second power mode; and the bias current has the second magnitude in response to the enable signals designating the third power mode.

19. The receiver circuit of claim 14, wherein the three or more signals are based on a mobile industry processor interface (MIPI)C-PHY protocol.

20. A receiver circuit comprising: a plurality of data lane modules, each of the plurality of data lane modules configured to receive respective data signals; a clock lane module configured to receive clock signals and configured to provide each of the plurality of data lane modules with a respective divided clock signal among divided clock signals based on the clock signals; a bias current controller configured to control a clock bias current provided to the clock lane module; and a link layer configured to provide a bias control signal to the bias current controller and configured to provide clock gating signals to the clock lane module, based on a power mode of the clock lane module and the plurality of data lane modules, the power mode being determined based on levels of low power data signals output from the plurality of data lane modules and low power clock signals output from the clock lane module, wherein the bias current controller, based on the bias control signal, is configured to: cut off the clock bias current in a first power mode; provide the clock bias current having a first magnitude to the clock lane module in a second power mode; and provide the clock bias current having a second magnitude greater than the first magnitude to the clock lane module in a third power mode, wherein in the second power mode, the clock lane module is configured to generate the divided clock signals provided to the plurality of data lane modules based on the clock gating signals, and wherein in the second power mode, the clock lane module operates in a high speed mode and the plurality of data lane modules operate in a low power mode.