System on Chip for Reducing Wake-Up Time, Method of Operating Same, and Computer System Including Same

1. A computer system comprising: an application processor including a read-only memory (ROM) configured to store a first boot loader, a first memory configured to store a second boot loader, and a second memory configured to store a third boot loader; and a power management integrated circuit (PMIC) configured to supply first power only to the second memory during a power-down mode, and supply second power to both the first and second memories during a wake-up mode, and wherein the application processor is configured to: receive an interrupt signal during the power-down mode; and perform a secure boot operation of the third boot loader based on the interrupt signal.

2. The computer system of claim 1, wherein the second memory is an always-on memory activated during the power-down mode and the wake-up mode.

3. The computer system of claim 1, wherein the first memory is a first static random access memory (SRAM), and the second memory is a second SRAM.

4. The computer system of claim 1, wherein the secure boot operation includes an integrity checking of the third boot loader.

5. The computer system of claim 4, wherein the application processor is further configured to stop the secure boot operation of the third boot loader in response to a failure of the integrity checking of the third boot loader.

6. The computer system of claim 1, wherein the application processor is further configured to: load the application processer, the second boot loader to the first memory after performing the secure boot operation of the third boot loader; jump to a first address of the second boot loader of the first memory; and execute the second boot loader of the first memory by using the first address.

7. The computer system of claim 6, further comprising a main memory, and wherein the application processor is further configured to: load an operating system (OS) to the main memory using the executed second boot loader; jump to a second address of the OS loaded on the main memory; and executing the OS by using the second address.

8. The computer system of claim 7, wherein an operation state of the OS is restored to a previous operation state prior to entering the power-down mode.

9. The computer system of claim 7, wherein the application processor is further configured to execute an application after executing the OS.

10. The computer system of claim 7, wherein the main memory is a dynamic random access memory (DRAM) external to the application processor.

11. The computer system of claim 1, wherein the performing the secure boot operation of the third boot loader includes: executing, by the application processor, the secure boot operation of the third boot loader of the second memory based on the interrupt signal.

12. The computer system of claim 1, wherein, before receiving the interrupt signal, the application processor is further configured to: perform a booting sequence; and entering to the power-down mode after performing the booting sequence.

13. The computer system of claim 1, wherein the first boot loader is used for selecting a booting device, wherein the second boot loader is used for a booting sequence, and wherein the third boot loader is used for a wake-up sequence.

14. The computer system of claim 1, wherein the power-down mode includes at least one of a low power mode, a sleep mode, a standby mode, and a suspend mode.

15. A computer system comprising: a system on chip (SoC) including a read-only memory (ROM) configured to store a first boot loader, a first memory configured to store a second boot loader, and a second memory configured to store a third boot loader; and a power management integrated circuit (PMIC) configured to supply first power only to the second memory during a power-down mode, and supply second power to both the first and second memories during a wake-up mode, and wherein the SoC is configured to: receive an interrupt signal during the power-down mode; perform a secure boot operation of the third boot loader; based on the interrupt signal; load the second boot loader to the first memory using the first boot loader after performing the secure boot operation of the third boot loader used for a wake-up sequence; execute the second boot loader of the first memory; and load an operating system (OS) to the main memory using the executed second boot loader.

16. The computer system of claim 15, wherein the secure boot operation includes an integrity checking of the third boot loader.

17. A method of operating a computer system including an application processor including a first memory and a second memory, and a power management integrated circuit (PMIC) configured to supply power to the second memory during a power-down mode and a wake-up mode, the method comprising: receiving, by the application processor, an interrupt signal during the power-down mode; and performing, by the application processor, a secure boot operation based on the interrupt signal during the wake-up mode.

18. The method of claim 17, wherein the application processor further includes a read-only memory (ROM), wherein the ROM is configured to store a first boot loader used for selecting a booting device, wherein the first memory is a first static random access memory (SRAM) configured to store a second boot loader used for a booting sequence, and wherein the second memory is a second SRAM configured to store a third boot loader used for a wake-up sequence corresponding to the wake-up mode.

19. The method of claim 18, wherein the performing, by the application processor, the secure boot operation based on the interrupt signal during the wake-up mode includes: loading, by the application processor, the third boot loader to the second memory for performing the secure boot operation; jumping, by the application processor, to a first address of the third boot loader of the second memory; and executing, by the application processor, the third boot loader of the second memory by using the first address.

20. The method of claim 19, wherein the computing system further includes a main memory, and wherein the method further comprises: loading, by the application processor, an operating system (OS) to the main memory based on the executed third boot loader; jumping, by the application processor, to a second address of the OS loaded on the main memory; executing, by the application processor, the OS by using the second address.