Pixel Driving Circuit and Display Panel

1. A pixel driving circuit, comprising: a light-emitting module, an external detection module, and an internal compensation module, wherein the light-emitting module is electrically connected to the external detection module and the internal compensation module; wherein the light-emitting module comprises a second transistor and a light-emitting unit, a first electrode of the second transistor is electrically connected to a high-electric potential power supply signal, and a second electrode of the second transistor is electrically connected to the light-emitting unit; the external detection module is configured to acquire a threshold voltage of the second transistor when a display panel is turned on, and determine a shift direction of the threshold voltage; and the internal compensation module is configured to use a first timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a positive shift; the internal compensation module is configured to use a second timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a negative shift; and the first timing sequence is different from the second timing sequence; wherein the pixel driving circuit is a 9T3C circuit, the light-emitting module further comprises a first transistor, a third transistor, and a first capacitor, a gate of the first transistor is input with a first light-emitting signal, a first electrode of the first transistor is input with a high-electric potential power supply signal, a second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to a second electrode of the third transistor, a first electrode of the third transistor is connected to an anode of the light-emitting unit, a gate of the third transistor is input with a second light-emitting signal, a cathode of the light-emitting unit is input with a low-electric potential power supply signal, one terminal of the first capacitor is connected to the first electrode of the first transistor, and another terminal of the first capacitor is connected to the second electrode of the second transistor; the external detection module comprises a first switch, a second switch, a chip, and a fourth transistor, a gate of the fourth transistor is input with a first scan signal, and a second electrode of the fourth transistor is electrically connected to the second electrode of the second transistor, a first electrode of the fourth transistor is connected to the chip through a first branch and a second branch arranged in parallel, the first branch comprises the first switch, and the second branch comprises the second switch; the internal compensation module comprises a third capacitor, a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, one terminal of the third capacitor is connected to a gate of the second transistor, and another terminal of the third capacitor is connected to the second electrode of the second transistor, a gate of the fifth transistor is input with the first scan signal, a second electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor, a first electrode of the fifth transistor is connected to the second electrode of the first transistor, a first electrode of the ninth transistor is connected to the first electrode of the first transistor, and a gate of the ninth transistor is input with a third scan signal, a second electrode of the seventh transistor is connected to the second electrode of the ninth transistor, a first electrode of the seventh transistor is electrically connected to the gate of the second transistor, a gate of the seventh transistor is input with a fourth scan signal, a gate of the eighth transistor is input with a fifth scan signal, a first electrode of the eighth transistor is input with a second data signal, and a second electrode of the eighth transistor is connected to the gate of the second transistor.

2. The pixel driving circuit of claim 1, wherein the positive shift of the shift direction of the threshold voltage means that the threshold voltage is greater than or equal to 0; and the negative shift of the shift direction of the threshold voltage means that the threshold voltage is less than 0.

3. The pixel driving circuit of claim 1, wherein when the threshold voltage is greater than or equal to 0, the internal compensation module is configured to use the first timing sequence to compensate the threshold voltage, and a compensation range of the threshold voltage is a first range; and when the threshold voltage is less than 0, the internal compensation module is configured to use the second timing sequence to compensate the threshold voltage, the compensation range of the threshold voltage is a second range, and the first range is different from the second range.

4. The pixel driving circuit of claim 3, wherein the first range ranges from 0 to 4V, and the second range ranges from −3V to 2V.

5. The pixel driving circuit of claim 1, further comprising a reset module, wherein the reset module comprises a sixth transistor and a second capacitor, a gate of the sixth transistor is input with a second scan signal, a second electrode of the sixth transistor is connected to the anode of the light-emitting unit and the second capacitor, and a first electrode of the sixth transistor is input with a reset signal.

6. The pixel driving circuit of claim 5, wherein working stages of the external detection module comprises an initialization stage, a storage stage, and a detection stage; in the initialization stage, the external detection module resets a potential of a G-point at the gate and a potential of an S-point at the second electrode of the second transistor; in the storage stage, the external detection module charges the second electrode of the second transistor to turn off the second transistor; and in the detection stage, the external detection module reads the threshold voltage of the second transistor.

7. The pixel driving circuit of claim 6, wherein in the initialization stage, the first scan signal and the fifth scan signal are at a high potential, the fourth transistor is turned on, the eighth transistor is turned on, the second data signal is at a low potential, the low potential VdataL of the second data signal is written to the G-point at the gate of the second transistor, a constant reference voltage Vref is written to the S-point at the second electrode of the second transistor, and at this time, the potential Vg of the G-point and the potential Vs of the S-point are initialized, where Vs=Vref and Vg=VdataL; in the storage stage, the fifth scan signal is at the high potential, the eighth transistor is turned on, the second data signal is at the high potential, and at this time, the high potential VdataH of the second data signal is written to the G-point, the second transistor is turned on, and the S-point starts to be charged; when Vs=VdataH−Vth, the second transistor is turned off, wherein the threshold voltage of the second transistor is Vth, and the potential of the S-point is charged to Vs=VdataH−Vth; and in the detection stage, the first scan signal is at the high potential, the fourth transistor is turned on, the first switch is turned off, the first data signal is not input, and the second switch is turned on, so that the chip reads the potential of the S-point and acquires the threshold voltage Vth of the second transistor.

8. The pixel driving circuit of claim 7, wherein when the Vth>0, the internal compensation module uses the first timing sequence to compensate the threshold voltage, and working stages of the first timing sequence comprises a first reset stage, a writing and compensation stage, and a first light-emitting stage; in the first reset stage, the third scan signal and the fourth scan signal are at the high potential, the seventh transistor and the ninth transistor are turned on, the high-electric potential power supply signal VDD is written to the G-point, the second scan signal is at the high potential, the sixth transistor is turned on, the reset signal Vi is written to an A-point connecting the second capacitor and the first electrode of the sixth transistor, and at this time, the potential of the G-point is Vg=VDD, and the potential Va of the A-point is equal to the Vi; in the writing and compensation stage, the first light-emitting signal, the first scan signal, the second scan signal, the fourth scan signal, and the fifth scan signal are at the high potential, the first switch, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all turned on, the high potential VDataH′ of the first data signal is written to the S-point, and at this time, the potential of the G-point is a sum of the potential of the S-point and the threshold voltage of the second transistor, and the potential of the A-point maintains at the Vi; and in the first light-emitting stage, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, the first transistor, the second transistor, and the third transistor are turned on, the potential Va of the A-point is equal to a sum of a voltage VF,LED of the light-emitting unit, the low-electric potential power supply signal VSS, and a voltage VIR(VSS) of a wiring connecting the A-point and the light-emitting unit, the fourth scan signal is at the high potential, the seventh transistor is turned on, the potential of the G-point is increased by the potential of the A-point through the second capacitor, at this time, the potential of the G-point is Vg=VDataH′+Vth−Vinit+VF,LED+VSS+VIR(VSS), and the potential Vs of the S-point is equal to a sum of the voltage VF,LED of the light-emitting unit, a divided voltage VT3 of the third transistor, the voltage VSS of the low-electric potential power supply signal, and a voltage VIR(VSS)′ of a wiring connecting the S-point and the light-emitting unit.

9. The pixel driving circuit of claim 7, wherein when Vth<0, the internal compensation module uses the second timing sequence to compensate the threshold voltage, working stages of the second timing sequence comprises a second reset stage, an acquisition and storage stage, a data writing stage, and a second light-emitting stage; in the second reset stage, the first scan signal and the fifth scan signal are at the high potential, the first switch is turned on, the fourth transistor is turned on, a Vneg signal carried by the first data signal is written into the potential of the S-point, the eighth transistor is turned on, a Vpre signal carried by the second data signal is written into the potential of the G-point to initialize the potentials of the G-point and the S-point, wherein Vg=Vpre and Vs=Vneg; in the acquisition and storage stage, the first scan signal, the fourth scan signal, the fifth scan signal, and the second data signal are at the high potential, the second transistor, the fifth transistor, and the seventh transistor are turned on; after the potential of the S-point is charged to VS=Vpre−Vth, the second transistor is turned off, the S-point stops being charged, and the potential of the S-point maintains at Vs=Vpre−Vth; in the data writing stage, the second data signal carries the high potential Vdata2, the fifth scan signal is at the high potential, the eighth transistor is turned on, the potential of the G-point is Vdata2, the second transistor is turned on, a coupling of the G-point through the third capacitor increases the potential of the S-point, at this time, the potential of the S-point is Vs=(Vpre−Vth)+(Vdata2−Vpre)*C3/(C1+C3), a potential difference between the G-point and the S-point is Vgs=(Vdata2−Vpre)*C1/(C1+C3)+Vth, wherein C1 is a capacitance value of the first capacitor and C3 is a capacitance value of the third capacitor; and in the second light-emitting stage, the potentials of the G-point and the S-point are maintained, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, and the first transistor, the second transistor, and the third transistor are turned on to cause the light-emitting unit to emit light.

10. A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises a light-emitting module, an external detection module, and an internal compensation module, the light-emitting module is electrically connected to the external detection module and the internal compensation module; wherein the light-emitting module comprises a second transistor and a light-emitting unit, a first electrode of the second transistor is electrically connected to a high-electric potential power supply signal, and a second electrode of the second transistor is electrically connected to the light-emitting unit; the external detection module is configured to acquire a threshold voltage of the second transistor when a display panel is turned on, and determine a shift direction of the threshold voltage; and the internal compensation module is configured to use a first timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a positive shift; the internal compensation module is configured to use a second timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a negative shift; and the first timing sequence is different from the second timing sequence; wherein the pixel driving circuit is a 9T3C circuit, the light-emitting module further comprises a first transistor, a third transistor, and a first capacitor, a gate of the first transistor is input with a first light-emitting signal, a first electrode of the first transistor is input with a high-electric potential power supply signal, a second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to a second electrode of the third transistor, a first electrode of the third transistor is connected to an anode of the light-emitting unit, a gate of the third transistor is input with a second light-emitting signal, a cathode of the light-emitting unit is input with a low-electric potential power supply signal, one terminal of the first capacitor is connected to the first electrode of the first transistor, and another terminal of the first capacitor is connected to the second electrode of the second transistor; the external detection module comprises a first switch, a second switch, a chip, and a fourth transistor, a gate of the fourth transistor is input with a first scan signal, and a second electrode of the fourth transistor is electrically connected to the second electrode of the second transistor, a first electrode of the fourth transistor is connected to the chip through a first branch and a second branch arranged in parallel, the first branch comprises the first switch, and the second branch comprises the second switch; the internal compensation module comprises a third capacitor, a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, one terminal of the third capacitor is connected to a gate of the second transistor, and another terminal of the third capacitor is connected to the second electrode of the second transistor, a gate of the fifth transistor is input with the first scan signal, a second electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor, a first electrode of the fifth transistor is connected to the second electrode of the first transistor, a first electrode of the ninth transistor is connected to the first electrode of the first transistor, and a gate of the ninth transistor is input with a third scan signal, a second electrode of the seventh transistor is connected to the second electrode of the ninth transistor, a first electrode of the seventh transistor is electrically connected to the gate of the second transistor, a gate of the seventh transistor is input with a fourth scan signal, a gate of the eighth transistor is input with a fifth scan signal, a first electrode of the eighth transistor is input with a second data signal, and a second electrode of the eighth transistor is connected to the gate of the second transistor.

11. The display panel of claim 10, wherein the positive shift of the shift direction of the threshold voltage means that the threshold voltage is greater than or equal to 0; and the negative shift of the shift direction of the threshold voltage means that the threshold voltage is less than 0.

12. The display panel of claim 10, wherein when the threshold voltage is greater than or equal to 0, the internal compensation module is configured to use the first timing sequence to compensate the threshold voltage, and a compensation range of the threshold voltage is a first range; and when the threshold voltage is less than 0, the internal compensation module is configured to use the second timing sequence to compensate the threshold voltage, the compensation range of the threshold voltage is a second range, and the first range is different from the second range.

13. The display panel of claim 12, wherein the first range ranges from 0 to 4V, and the second range ranges from −3V to 2V.

14. The display panel of claim 10, wherein the pixel driving circuit further comprises a reset module, the reset module comprises a sixth transistor and a second capacitor, a gate of the sixth transistor is input with a second scan signal, a second electrode of the sixth transistor is connected to the anode of the light-emitting unit and the second capacitor, and a first electrode of the sixth transistor is input with a reset signal.

15. The display panel of claim 14, wherein working stages of the external detection module comprises an initialization stage, a storage stage, and a detection stage; in the initialization stage, the external detection module resets a potential of a G-point at the gate and a potential of an S-point at the second electrode of the second transistor; in the storage stage, the external detection module charges the second electrode of the second transistor to turn off the second transistor; and in the detection stage, the external detection module reads the threshold voltage of the second transistor.

16. The display panel of claim 15, wherein in the initialization stage, the first scan signal and the fifth scan signal are at a high potential, the fourth transistor is turned on, the eighth transistor is turned on, the second data signal is at a low potential, the low potential VdataL of the second data signal is written to the G-point at the gate of the second transistor, a constant reference voltage Vref is written to the S-point at the second electrode of the second transistor, and at this time, the potential Vg of the G-point and the potential Vs of the S-point are initialized, where Vs=Vref and Vg=VdataL; in the storage stage, the fifth scan signal is at the high potential, the eighth transistor is turned on, the second data signal is at the high potential, and at this time, the high potential VdataH of the second data signal is written to the G-point, the second transistor is turned on, and the S-point starts to be charged; when Vs=VdataH−Vth, the second transistor is turned off, wherein the threshold voltage of the second transistor is Vth, and the potential of the S-point is charged to Vs=VdataH−Vth; and in the detection stage, the first scan signal is at the high potential, the fourth transistor is turned on, the first switch is turned off, the first data signal is not input, and the second switch is turned on, so that the chip reads the potential of the S-point and acquires the threshold voltage Vth of the second transistor.

17. The display panel of claim 16, wherein when the Vth>0, the internal compensation module uses the first timing sequence to compensate the threshold voltage, and working stages of the first timing sequence comprises a first reset stage, a writing and compensation stage, and a first light-emitting stage; in the first reset stage, the third scan signal and the fourth scan signal are at the high potential, the seventh transistor and the ninth transistor are turned on, the high-electric potential power supply signal VDD is written to the G-point, the second scan signal is at the high potential, the sixth transistor is turned on, the reset signal Vi is written to an A-point connecting the second capacitor and the first electrode of the sixth transistor, and at this time, the potential of the G-point is Vg=VDD, and the potential Va of the A-point is equal to the Vi; in the writing and compensation stage, the first light-emitting signal, the first scan signal, the second scan signal, the fourth scan signal, and the fifth scan signal are at the high potential, the first switch, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all turned on, the high potential VDataH′ of the first data signal is written to the S-point, and at this time, the potential of the G-point is a sum of the potential of the S-point and the threshold voltage of the second transistor, and the potential of the A-point maintains at the Vi; and in the first light-emitting stage, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, the first transistor, the second transistor, and the third transistor are turned on, the potential Va of the A-point is equal to a sum of a voltage VF,LED of the light-emitting unit, the low-electric potential power supply signal VSS, and a voltage VIR(VSS) of a wiring connecting the A-point and the light-emitting unit, the fourth scan signal is at the high potential, the seventh transistor is turned on, the potential of the G-point is increased by the potential of the A-point through the second capacitor, at this time, the potential of the G-point is Vg=VDataH′+Vth−Vinit+VF,LED+VSS+VIR(VSS), and the potential Vs of the S-point is equal to a sum of the voltage VF,LED of the light-emitting unit, a divided voltage VT3 of the third transistor, the voltage VSS of the low-electric potential power supply signal, and a voltage VIR(VSS)′ of a wiring connecting the S-point and the light-emitting unit.

18. The display panel of claim 16, wherein when Vth<0, the internal compensation module uses the second timing sequence to compensate the threshold voltage, working stages of the second timing sequence comprises a second reset stage, an acquisition and storage stage, a data writing stage, and a second light-emitting stage; in the second reset stage, the first scan signal and the fifth scan signal are at the high potential, the first switch is turned on, the fourth transistor is turned on, a Vneg signal carried by the first data signal is written into the potential of the S-point, the eighth transistor is turned on, a Vpre signal carried by the second data signal is written into the potential of the G-point to initialize the potentials of the G-point and the S-point, wherein Vg=Vpre and Vs=Vneg; in the acquisition and storage stage, the first scan signal, the fourth scan signal, the fifth scan signal, and the second data signal are at the high potential, the second transistor, the fifth transistor, and the seventh transistor are turned on; after the potential of the S-point is charged to VS=Vpre−Vth, the second transistor is turned off, the S-point stops being charged, and the potential of the S-point maintains at Vs=Vpre−Vth; in the data writing stage, the second data signal carries the high potential Vdata2, the fifth scan signal is at the high potential, the eighth transistor is turned on, the potential of the G-point is Vdata2, the second transistor is turned on, a coupling of the G-point through the third capacitor increases the potential of the S-point, at this time, the potential of the S-point is Vs=(Vpre−Vth)+(Vdata2−Vpre)*C3/(C1+C3), a potential difference between the G-point and the S-point is Vgs=(Vdata2−Vpre)*C1/(C1+C3)+Vth, wherein C1 is a capacitance value of the first capacitor and C3 is a capacitance value of the third capacitor; and in the second light-emitting stage, the potentials of the G-point and the S-point are maintained, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, and the first transistor, the second transistor, and the third transistor are turned on to cause the light-emitting unit to emit light.