Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first chip; a second chip; a third chip; and a fourth chip, wherein the first chip is placed adjacent to the second chip and the fourth chip, the third chip is placed adjacent to the second chip and the fourth chip at a position different from a position of the first chip, data of the first chip is transferred from the first chip to the third chip via the second chip, data of the third chip is transferred from the third chip to the first chip via the fourth chip, and data of the first chip transferred from the first chip to the third chip via the second chip and used in an arithmetic operation by an internal circuit of the third chip is not used in an arithmetic operation by an internal circuit of the second chip.
2. The semiconductor device as claimed in claim 1, wherein each of the first chip, the second chip, the third chip, and the fourth chip is shaped as a rectangle with four edges in a planar view, an edge of one chip of adjacent chips faces an edge of another chip of the adjacent chips.
3. The semiconductor device as claimed in claim 1, wherein data of the second chip is transferred to the fourth chip via the third chip, and data of the fourth chip is transferred to the second chip via the first chip, data of the second chip transferred from the second chip to the fourth chip via the third chip and used in an arithmetic operation by an internal circuit of the fourth chip is not used in an arithmetic operation by an internal circuit of the third chip.
4. The semiconductor device as claimed in claim 1, wherein data of the second chip is transferred to the fourth chip via the third chip, and data of the fourth chip is transferred to the second chip via the first chip.
5. The semiconductor device as claimed in claim 1, wherein each of the second chip and the fourth chip includes an error detection circuit.
6. The semiconductor device as claimed in claim 1, wherein a line including two comers of the first chip overlaps the third chip.
7. The semiconductor device as claimed in claim 1, wherein a layout design of the first chip is the same as a layout design of the third chip.
8. The semiconductor device as claimed in claim 7, wherein a layout design of the second chip is the same as a layout design of the fourth chip.
9. The semiconductor device as claimed in claim 1, wherein the data transferred from the first chip to the second chip is transferred via a silicon interposer.
10. The semiconductor device as claimed in claim 1, wherein the data is transferred from the first chip to the third chip via the second chip without performing an arithmetic operation by an internal circuit of the second chip, and an internal circuit of the third chip performs an arithmetic operation on the data transferred from the first chip to the third chip via the second chip.
11. A data transfer method for a semiconductor device including a first chip, a second chip, a third chip, and, a fourth chip, the data transfer method comprising: transferring data of the first chip from the first chip to the third chip via the second chip, transferring data of the third chip from the third chip to the first chip via the fourth chip, and wherein the first chip is placed adjacent to the second chip and the fourth chip, the third chip is placed adjacent to the second chip and the fourth chip at a position different from a position of the first chip, and data of the first chip transferred from the first chip to the third chip via the second chip and used in an arithmetic operation by an internal circuit of the third chip is not used in an arithmetic operation by an internal circuit of the second chip.
12. The data transfer method as claimed in claim 11, wherein each of the first chip, the second chip, the third chip, and the fourth chip is shaped as a rectangle with four edges in a planar view, an edge of one chip of adjacent chips faces an edge of another chip of the adjacent chips.
13. The data transfer method as claimed in claim 11, further comprising: transferring data of the second chip to the fourth chip via the third chip, and transferring data of the fourth chip to the second chip via the first chip. wherein data of the second chip transferred from the second chip to the fourth chip via the third chip and used in an arithmetic operation by an internal circuit of the fourth chip is not used in an arithmetic operation by an internal circuit of the third chip.
14. The data transfer method as claimed in claim 11, further comprising: transferring data of the second chip to the fourth chip via the third chip, and transferring data of the fourth chip to the second chip via the first chip.
15. The data transfer method as claimed in claim 11, wherein each of the second chip and the fourth chip includes an error detection circuit.
16. The data transfer method as claimed in claim 11, wherein a line including two corners of the first chip overlaps the third chip.
17. The data transfer method as claimed in claim 11, wherein a layout design of the first chip is the same as a layout design of the third chip.
18. The data transfer method as claimed in claim 17, wherein a layout design of the second chip is the same as a layout design of the fourth chip.
19. The data transfer method as claimed in claim 11, wherein the data transferred from the first chip to the second chip is transferred via a silicon interposer.
20. The data transfer method as claimed in claim 11, wherein the data is transferred from the first chip to the third chip via the second chip without performing an arithmetic operation by an internal circuit of the second chip, and an internal circuit of the third chip performs an arithmetic operation on the data transferred from the first chip to the third chip via the second chip.
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March 18, 2025
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