Dynamic DDR Scaling And Use Case Management Based On DDR Refresh Rate And Size

1. A method for scaling memory frequency configuration of a memory of a computing device, comprising: obtaining a set of real-time use case parameters for a use case while the use case is executed by the computing device, wherein the set of real-time use case parameters includes at least a memory refresh rate of the memory, a memory size of the memory, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC; comparing the set of real-time use case parameters with a stored set of use case parameters, wherein the stored set of use case parameters include at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC; selecting a memory frequency based on a result of the comparison; and configuring the memory to operate at the memory frequency for the execution of the use case by the computing device.

2. The method of claim 1, wherein: the at least one use case bandwidth comprises a use case current bandwidth and a use case average bandwidth; and the at least one stored use case bandwidth comprises a stored use case current bandwidth and a stored use case average bandwidth.

3. The method of claim 1, further comprising: identifying a stored memory refresh rate matching the memory refresh rate; identifying a stored memory size matching the memory size; identifying the at least one stored use case bandwidth matching the at least one use case bandwidth; identifying the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency; and identifying the memory frequency stored in association with the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency.

4. The method of claim 1, further comprising identifying a maximum memory frequency as the memory frequency in response to failing to identify at least one of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises less than all of the at least one stored use case bandwidth matching the use case bandwidth or the at least one stored use case latency matching the use case latency.

5. The method of claim 1, further comprising issuing an alarm signal configured to indicate changing the use case for the memory to be able to achieve a use case parameter.

6. The method of claim 1, further comprising receiving the memory refresh rate from a memory sub-system.

7. The method of claim 1, further comprising transmitting a memory frequency modification signal to a memory sub-system.

8. A computing device, comprising: a memory frequency device configured to: obtain a set of real-time use case parameters for a use case while the use case is executed by the computing device, wherein the set of real-time use case parameters includes at least a memory refresh rate of the memory, a memory size of the memory, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC; compare the set of real-time use case parameters with a stored set of use case parameters, wherein the stored set of use case parameters include at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC; select a memory frequency based on a result of the comparison; and configure the memory to operate at the memory frequency for the execution of the use case by the computing device.

9. The computing device of claim 8, wherein the memory frequency device is configured such that: the at least one use case bandwidth comprises a use case current bandwidth and a use case average bandwidth; and the at least one stored use case bandwidth comprises a stored use case current bandwidth and a stored use case average bandwidth.

10. The computing device of claim 8, wherein the memory frequency device is further configured to: identify a stored memory refresh rate matching the memory refresh rate; identify a stored memory size matching the memory size; identify the at least one stored use case bandwidth matching the at least one use case bandwidth; identify the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency; and identify the memory frequency stored in association with the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency.

11. The computing device of claim 8, wherein the memory frequency device is further configured to identify a maximum memory frequency as the memory frequency in response to failing to identify at least one of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises less than all of the at least one stored use case bandwidth matching the use case bandwidth or the at least one stored use case latency matching the use case latency.

12. The computing device of claim 8, wherein the memory frequency device is further configured to issue an alarm signal configured to indicate changing the use case for the memory to be able to achieve a use case parameter.

13. The computing device of claim 8, wherein the memory frequency device is further configured to receive the memory refresh rate from a memory sub-system.

14. The computing device of claim 8, wherein the memory frequency device is further configured to transmit a memory frequency modification signal to a memory sub-system.

15. A computing device, comprising: means for obtaining a set of real-time use case parameters for a use case while the use case is executed by the computing device, wherein the set of real-time use case parameters includes at least a memory refresh rate of the memory, a memory size of the memory, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC; means for comparing the set of real-time use case parameters with a stored set of use case parameters, wherein the stored set of use case parameters include at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC; means for selecting a memory frequency based on a result of the comparison; and means for configuring the memory to operate at the memory frequency for the execution of the use case by the computing device.

16. The computing device of claim 15, wherein: the at least one use case bandwidth comprises a use case current bandwidth and a use case average bandwidth; and the at least one stored use case bandwidth comprises a stored use case current bandwidth and a stored use case average bandwidth.

17. The computing device of claim 15, further comprising: means for identifying a stored memory refresh rate matching the memory refresh rate; means for identifying a stored memory size matching the memory size; means for identifying the at least one stored use case bandwidth matching the at least one use case bandwidth; means for identifying the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency; and means for identifying the memory frequency stored in association with the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency.

18. The computing device of claim 15, further comprising means for identifying a maximum memory frequency as the memory frequency in response to failing to identify at least one of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises less than all of the at least one stored use case bandwidth matching the use case bandwidth or the at least one stored use case latency matching the use case latency.

19. The computing device of claim 15, further comprising means for issuing an alarm signal configured to indicate changing the use case for the memory to be able to achieve a use case parameter.

20. The computing device of claim 15, further comprising means for receiving the memory refresh rate from a memory sub-system.

21. The computing device of claim 15, further comprising means for transmitting a memory frequency modification signal to a memory sub-system.

22. A non-transitory processor-readable medium having stored thereon processor executable instructions configured to cause a memory frequency device of a computing device to perform operations comprising: obtaining a set of real-time use case parameters for a use case while the use case is executed by the computing device, wherein the set of real-time use case parameters includes at least a memory refresh rate of the memory, a memory size of the memory, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC; comparing the set of real-time use case parameters with a stored set of use case parameters, wherein the stored set of use case parameters include at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC; selecting a memory frequency based on a result of the comparison; and configuring the memory to operate at the memory frequency for execution of the use case by the computing device.

23. The non-transitory processor-readable medium of claim 22, wherein: the at least one use case bandwidth comprises a use case current bandwidth and a use case average bandwidth; and the at least one stored use case bandwidth comprises a stored use case current bandwidth and a stored use case average bandwidth.

24. The non-transitory processor-readable medium of claim 22, wherein the stored processor executable instructions are configured to cause the memory frequency device to perform operations further comprising: identifying a stored memory refresh rate matching the memory refresh rate; identifying a stored memory size matching the memory size; identifying the at least one stored use case bandwidth matching the at least one use case bandwidth; identifying the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency; and identifying the memory frequency stored in association with the stored memory refresh rate, the stored memory size, the at least one stored use case bandwidth, and the at least one stored use case latency.

25. The non-transitory processor-readable medium of claim 22, wherein the stored processor executable instructions are configured to cause the memory frequency device to perform operations further comprising identifying a maximum memory frequency as the memory frequency in response to failing to identify at least one of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case latency matching the use case latency, wherein the result of the comparison comprises less than all of the at least one stored use case bandwidth matching the use case bandwidth or the at least one stored use case latency matching the use case latency.

26. The non-transitory processor-readable medium of claim 22, wherein the stored processor executable instructions are configured to cause the memory frequency device to perform operations further comprising issuing an alarm signal configured to indicate changing the use case for the memory to be able to achieve a use case parameter.

27. The non-transitory processor-readable medium of claim 22, wherein the stored processor executable instructions are configured to cause the memory frequency device to perform operations further comprising receiving the memory refresh rate from a memory sub-system.

28. The non-transitory processor-readable medium of claim 22, wherein the stored processor executable instructions are configured to cause the memory frequency device to perform operations further comprising transmitting a memory frequency modification signal to a memory sub-system.