Methods and Apparatus for Integrated Image Signal Processing

1. A method comprising: obtaining a first image data in a first format from a first image sensor connected directly to the computerized device; programming a first reprogrammable processing device (RPD) to perform a first operation on at least a portion of the first image data; processing the at least a portion of the first image data using the programmed first RPD to generate first output data, wherein the programming and the processing of the at least a portion of the first image data using the programmed first RPD are performed during a first time slot; reprogramming the first RPD to perform a second operation on at least a portion of the first output data; and processing the at least a portion of the first output data using the reprogrammed first RPD to generate second output data, wherein the reprogramming and the processing of the at least a portion of the first output data using the reprogrammed first RPD are performed during a second time slot subsequent to the first time slot, wherein the first and second time slots have a same temporal duration; obtaining second image data from a second image sensor; programming a second RPD to perform a third operation on at least a portion of the second image data; processing the at least a portion of the second image data using the second RPD to generate third output data; reprogramming the second RPD to perform a fourth operation on at least a portion of the third output data; and processing the at least a portion of the third output data using the second RPD to generate fourth output data.

2. The method of claim 1, wherein at least one of a duration or starting point of each the first and second time slots is generated ad hoc.

3. The method of claim 1, wherein the first and second time slots are each generated prior to the programming.

4. The method of claim 1, wherein the first and second time slots have a different temporal duration, and each comprise at least one prescribed mini-slot, the at least one mini-slot referenced to a clock reference of the RPD.

5. The method of claim 1, wherein: the obtaining image data in a first format from at least one image sensor comprises obtaining image data in a RAW format; the programming a reprogrammable processing device (RPD) to perform a first operation on at least a portion of the obtained image data comprises programming the reprogrammable processing device (RPD) to convert the at least a portion of the obtained image from the RAW format to an image format; and the reprogramming the RPD to perform a second operation on at least a portion of the first output data comprises programming the reprogrammable processing device (RPD) to apply a Bayer filter.

6. The method of claim 1, further comprising: reprogramming the RPD to perform a third operation on at least a portion of the second output data; and processing the at least a portion of the second output data using the reprogrammed RPD to generate third output data; wherein the third output data comprises encoded image data encoded according to a lossy encoding format.

7. Computerized apparatus, comprising: at least one image sensor; a first reprogrammable processing device (RPD) in data communication with the at least a first image sensor; at least one storage device in data communication with the first RPD; at least one controller in data communication with the first RPD and configured to implement computerized logic causing the first RPD device to at least: process first data output by the at least one image sensor using a first processing configuration to produce second data; process the second data using a second processing configuration to produce third data; and process the third data using a third processing configuration to produce fourth data, wherein the first RPD, the at least one storage device, and the at least one controller are each contained within a common integrated circuit (IC) package, and the at least one image sensor is directly connected to the common IC package; and a second RPD connected to a second image sensor, and the at least one storage device comprises a storage device in data communication with both of the first RPD and the second RPD.

8. The computerized apparatus of claim 7, wherein the at least one controller is further configured to implement computerized logic causing the first RPD device to at least: access at least a portion of the at least one storage device to obtain the first data; access at least a portion of the at least one storage device to obtain the second data; and access at least a portion of the at least one storage device to obtain the third data; wherein (i) each of the accesses to obtain the first data, second data, and third data; and (ii) each of the processing of the first data, second data, and third data, occur according to a schedule generated at least in part by the at least one controller.

9. The computerized apparatus of claim 7, wherein the first RPD comprises a plurality of circuit logic elements which may be logically combined in a plurality of different combinations, a first of the plurality of different combinations corresponding to the first processing configuration, a second of the plurality of different combinations corresponding to the second processing configuration, and a third of the plurality of different combinations corresponding to the third processing configuration.

10. The computerized apparatus of claim 9, wherein first RPD comprises a field programmable gate array (FPGA) apparatus comprising the plurality of circuit logic elements, at least portions of the circuit logic elements comprising logic rendered in hardware.

11. Integrated circuit apparatus comprising: at least one first data interface; at least one second data interface; a controller interface; and computerized logic configured to, under control of signals received via the controller interface: receive first data via the at least one first interface; process the first data using a first processing configuration to produce second data; output the second data to a storage device via the at least one second data interface; reconfigure the computerized logic to a second processing configuration; access the second data from the storage device via the at least one second interface; process the accessed second data using the second processing configuration to produce third data; output the third data to the storage device via the at least one second data interface; reconfigure the computerized logic to a third processing configuration; access the third data from the storage device via the at least one second interface; and process the accessed third data using the third processing configuration to produce fourth data, wherein the computerized logic is configured such that: at least the processing of the first data using a first processing configuration to produce the second data, and the output of the second data to the storage device via the at least one second data interface, occurs during a first time period; at least the access of the second data from the storage device via the at least one second interface, and the processing of the accessed second data using the second processing configuration to produce the third data, and the output the third data to the storage device via the at least one second data interface, occurs during a second time period; and at least the access of the third data from the storage device via the at least one second interface, and the processing of the accessed third data using the third processing configuration to produce the fourth data, occurs during a third time period, and wherein the first, second, and third time periods comprise non-overlapping time periods, wherein the first, second, and third time periods each have different temporal durations than one another.

12. The Integrated circuit apparatus of claim 11, further comprising: the storage device in data communication with the at least one second interface; and controller logic in communication with the controller interface; and wherein the storage device, the controller logic, the at least one first data interface, the at least one second data interface, the controller interface, and the computerized logic are all part of a unitary integrated circuit package.

13. The Integrated circuit apparatus of claim 12, wherein: the storage device comprises a dynamic RAM (random access memory) device; and the computerized logic comprises a reconfigurable processing fabric having a plurality of logic cells or blocks.

14. The Integrated circuit apparatus of claim 11, further comprising a clock circuit; and wherein the first, second, and third time periods each comprise an integer multiple of a clock period or other clock-related parameter generated by the clock circuit.

15. The Integrated circuit apparatus of claim 11, wherein the storage device comprises a plurality of independently accessible storage areas, the at least one second data interface comprising a plurality of second data interfaces corresponding to respective ones of the plurality of independently accessible storage areas.

16. The computerized apparatus of claim 7, wherein the at least one image sensor comprises a first image sensor and a second image sensor, wherein the first and second image sensors are directly connected to the common IC package and oriented in: a same direction as one another; or in different directions from one another.

17. The computerized apparatus of claim 7, wherein the at least one RPD is a first RPD, the first RPD is connected to the first image sensor, the computerized image capture and processing apparatus further comprises a second RPD connected to the second image sensor, and the at least one storage device comprises a storage device in data communication with both of the first RPD and the second RPD.

18. The method of claim 1, further comprising processing the second output data and the fourth output together to combine the second output data and the fourth output data into a common image.