Data Processing Array Event Trace Customization, Offload, and Analysis

1. A method, comprising: implementing a design for a data processing array of a target integrated circuit by, at least in part, adding a trace data offload architecture to the design; configuring one or more selected tiles of the data processing array used by the design as implemented in the target integrated circuit to generate trace data based on user-specified runtime settings for performing a trace; during execution of the design by the data processing array, conveying the trace data as generated by the one or more selected tiles of the data processing array to a memory of the target integrated circuit using the trace data offload architecture; and generating a trace report from the trace data using a data processing system coupled to the target integrated circuit, wherein the generating the trace report comprises analyzing the trace data using the user-specified runtime settings and metadata generated from compiling the design, wherein the trace report correlates trace events of the trace data with respective tiles of the one or more selected tiles of the data processing array.

2. The method of claim 1, further comprising: generating the metadata from compiling the design, wherein the metadata specifies correlations between different portions of the design and different tiles of the data processing array used by the design; and providing the metadata to a runtime executing on a processor system of the target integrated circuit, wherein the runtime performs the configuring of the one or more selected tiles of the data processing system.

3. The method of claim 1, further comprising: generating the metadata from the compiling, wherein the metadata specifies correlations between different portions of the design and different tiles of the data processing array used by the design; generating configuration data used to configure the one or more selected tiles of the data processing array based on the metadata; and providing the configuration data to the data processing array.

4. The method of claim 1, wherein the trace data offload architecture is capable of conveying one or more streams of the trace data from the data processing array through one or more data paths implemented in programmable logic.

5. The method of claim 1, wherein the implementing further comprises: routing a specified number of streams for conveying the trace data to the trace data offload architecture, wherein each tile of the data processing array used by the design is coupled to at least one of the streams.

6. The method of claim 5, further comprising: coupling the streams conveying trace data to one or more data movers of the trace data offload architecture.

7. The method of claim 5, further comprising: allocating buffers in the memory of the target integrated circuit for the streams.

8. The method of claim 7, wherein each buffer as allocated has a user-specified depth.

9. The method of claim 1, wherein the trace data offload architecture is capable of conveying one or more streams of the trace data from the data processing array through one or more direct memory access circuits.

10. The method of claim 1, wherein the trace report correlates the trace events with particular functions executed by the one or more selected tiles of the data processing array as specified by the metadata.

11. The method of claim 1, wherein the trace report correlates the trace events with a particular operation performed by a function executed by the one or more selected tiles of the data processing array as specified by the metadata.

12. The method of claim 1, wherein the user-specified runtime settings specify the trace events generated during the trace.

13. A system, comprising: an integrated circuit having: a data processing array including an array of tiles having a plurality of hardwired compute tiles each including a processor and a data memory, wherein the processor and the data memory of each compute tile comprises event logic and trace circuitry configured to generate trace events each associated with at least one of a timer value or a program counter value for the compute tile; a user-specified trace data offload architecture coupled to the data processing array; and a memory; wherein a plurality of active tiles of the array of tiles are used to execute a user design implemented in the data processing array; wherein one or more selected tiles of the plurality of active tiles are configured to generate trace data including the trace events during execution of the user design by the data processing array; and wherein the user-specified trace data offload architecture is configured to convey a plurality of streams of the trace data as generated by the one or more selected tiles to the memory.

14. The system of claim 13, wherein the user-specified trace data offload architecture comprises: one or more data paths implemented in programmable logic for the plurality of streams of the trace data.

15. The system of claim 13, wherein the user-specified trace data offload architecture comprises: one or more direct memory access circuits configured to convey the plurality of streams of the trace data.

16. The system of claim 13, further comprising: a data processing system configured to generate a trace report from the trace data.

17. The system of claim 16, wherein the data processing system is configured to generate the trace report by analyzing the trace data using user-specified runtime settings and metadata generated from compiling the user design to correlate trace events of the plurality of streams of the trace data with respective tiles of the one or more selected tiles.

18. The system of claim 17, wherein the data processing system is configured to generate the trace report by correlating the trace events with particular functions executed by the selected tiles as specified by the metadata.

19. The system of claim 17, wherein the data processing system is configured to generate the trace report by correlating the trace events with particular operations performed by particular functions executed by the selected tiles as specified by the metadata.

20. The system of claim 13, wherein the integrated circuit comprises: a network-on-chip, wherein the user-specified trace data offload architecture conveys the plurality of streams of the trace data from the data processing array to the network-on-chip; and a memory controller coupled to the network-on-chip, wherein the memory controller is configured to write the trace data received via the network-on-chip to the memory.