System-On-Chip with a Plurality of Chips Communicating Wirelessly Using Horizontal Inductive Coupling

1. An information processing apparatus, comprising: a plurality of chips including a first chip and a second chip; a pair of transmitting coil and receiving coil formed on each of the plurality of chips, each coil of the pair of transmitting coil and receiving coil being formed along a periphery of each of the plurality of chips to define an inner area of each of the plurality of chips in a plan view; and a transmitting/receiving circuit formed on each of the plurality of chips, the transmitting/receiving circuit being configured with a transmitting circuit including an inverter and a receiving circuit including a hysteresis comparator, the transmitting/receiving circuit being formed at the inner area, wherein the plurality of chips communicate with one another via a wireless connection based on inductive coupling in a horizontal direction between the transmitting coil of the first chip and the receiving coil of the second chip, and at least one of a core circuit and a network interface is formed at the inner area of one of the plurality of chips, and the inner area is located inside of each coil of the pair of transmitting coil and receiving coil of the one of the plurality of chips in the plan view.

2. The information processing apparatus according to claim 1, wherein: the plurality of chips are horizontally integrated on a substrate, and the substrate is a variable shape member.

3. The information processing apparatus according to claim 2, wherein: the variable shape member is a flexible substrate.

4. The information processing apparatus according to claim 2, wherein: the variable shape member is made of a plastic.

5. The information processing apparatus according to claim 2, wherein: the variable shape member is made of a fiber.

6. The information processing apparatus according to claim 1, wherein: a coil diameter of the pair of transmitting coil and receiving coil on the first chip is the same as a coil diameter of the pair of transmitting coil and receiving coil on the second chip.

7. The information processing apparatus according to claim 6, wherein: the transmitting coil and the receiving coil are formed on different layers of one of the plurality of chips.

8. The information processing apparatus according to claim 1, wherein: the inner area of the one of the plurality of chips is 80% or more of an area of the one of the plurality of chips.

9. The information processing apparatus according to claim 1, wherein: a seal ring is formed on each of the plurality of chips, and a part of the seal ring is divided.

10. The information processing apparatus according to claim 9, wherein: a thickness of the seal ring is 2 μm or less.

11. The information processing apparatus according to claim 1, wherein: a power ring is formed on each of the plurality of chips, and a distance between the pair of transmitting coil and receiving coil and the power ring is 150 μm or more.

12. The information processing apparatus according to claim 1, wherein: one of the plurality of chips is a CPU (Central Processing Unit).

13. The information processing apparatus according to claim 1, wherein: one of the plurality of chips is a memory.

14. The information processing apparatus according to claim 1, wherein: a hardware configuring the information processing apparatus is configured of one or more chips among the plurality of chips.

15. The information processing apparatus according to claim 14, wherein: the hardware is a CPU (Central Processing Unit).

16. The information processing apparatus according to claim 1, wherein: the plurality of chips are horizontally integrated.

17. The information processing apparatus according to claim 1, wherein: the plurality of chips are horizontally integrated on a substrate, the first chip is located directly adjacent to the second chip, and an extending direction of the first chip is inclined to an extending direction of the second chip.

18. The information processing apparatus according to claim 1, wherein: each coil of the pair of transmitting coil and receiving coil is ring-shaped, and the inner area of the one of the plurality of chips is surrounded by each coil of the pair of transmitting coil and receiving coil.

19. The information processing apparatus according to claim 9, wherein: the seal ring is located closer to the periphery of one of the plurality of chips than the pair of transmitting coil and receiving coil.

20. The information processing apparatus according to claim 11, wherein: the power ring is located in an enclosed area of one of the plurality of chips, and the enclosed area is surrounded by the pair of transmitting coil and receiving coil.