Pixel Circuit, Array Substrate and Display Panel

1. A pixel circuit, comprising: a pixel driving circuit; a bonding unit connected to the pixel driving circuit, wherein the bonding unit includes a first bonding terminal group and at least one second bonding terminal group that are arranged in parallel, and the first bonding terminal group and a second bonding terminal group are configured to bond light-emitting devices, wherein the first bonding terminal group includes a first terminal and a second terminal, and the second bonding terminal group includes a third terminal and a fourth terminal; the first terminal and the third terminal are connected, and are both connected to the pixel driving circuit; the second terminal and the fourth terminal are connected, and are both connected to a set voltage signal line.

2. The pixel circuit according to claim 1, wherein the pixel driving circuit is electrically connected to one of a first voltage signal line and a second voltage signal line, and the set voltage signal line is another one of the first voltage signal line and the second voltage signal line; wherein the first voltage signal line is configured to transmit a first voltage signal, the second voltage signal line is configured to transmit a second voltage signal, and a voltage of the first voltage signal is greater than a voltage of the second voltage signal.

3. The pixel circuit according to claim 2, further comprising an electrostatic protection circuit, wherein the first terminal and the third terminal are connected to a first connection node, and the electrostatic protection circuit is electrically connected to the first connection node; the electrostatic protection circuit includes a first electrostatic protection circuit, and the first electrostatic protection circuit includes a first sub-circuit and a second sub-circuit; a first terminal of the first sub-circuit and a second terminal of the second sub-circuit are electrically connected to a first connection point; a second terminal of the first sub-circuit is electrically connected to a third voltage signal line, and a first terminal of the second sub-circuit is electrically connected to a fourth voltage signal line; the third voltage signal line is configured to transmit a third voltage signal, and the fourth voltage signal line is configured to transmit a fourth voltage signal; a voltage of the third voltage signal is greater than a voltage of the fourth voltage signal; the first sub-circuit is configured to be turned on when an abnormal high voltage occurs at the first connection node, so that the first connection point discharges to the third voltage signal line; and the second sub-circuit is configured to be turned on when an abnormal low voltage occurs at the first connection node, so that the fourth voltage signal line charges the first connection point.

4. The pixel circuit according to claim 3, wherein the first sub-circuit includes at least one first transistor; the first sub-circuit includes one first transistor; a gate of the first transistor is electrically connected to a second electrode thereof, a first electrode of the first transistor is electrically connected to the first connection point, and the second electrode of the first transistor is electrically connected to the third voltage signal line; or the first sub-circuit includes at least two first transistors connected in series; a gate of each first transistor is electrically connected to a second electrode thereof, a first electrode of a first transistor in the at least two first transistors is electrically connected to the first connection point, and a second electrode of a last first transistor in the at least two first transistors is electrically connected to the third voltage signal line.

5. The pixel circuit according to claim 3, wherein the second sub-circuit includes at least one second transistor; the second sub-circuit includes one second transistor; a gate of the second transistor is electrically connected to a second electrode thereof, a first electrode of the second transistor is electrically connected to the fourth voltage signal line, and the second electrode of the second transistor is electrically connected to the first connection point; or the second sub-circuit includes at least two second transistors connected in series; a gate of each second transistor is electrically connected to a second electrode thereof, a first electrode of a first second transistor in the at least two second transistors is electrically connected to the fourth voltage signal line, and a second electrode of a last second transistor in the at least two second transistors is electrically connected to the first connection point.

6. The pixel circuit according to claim 3, wherein the second terminal and the fourth terminal are connected to a second connection node, and the electrostatic protection circuit is further electrically connected to the second connection node; the electrostatic protection circuit further includes a second electrostatic protection circuit, and the second electrostatic protection circuit includes a third sub-circuit and a fourth sub-circuit; a first terminal of the third sub-circuit and a second terminal of the fourth sub-circuit are electrically connected to a second connection point; a second terminal of the third sub-circuit is electrically connected to the third voltage signal line; a first terminal of the fourth sub-circuit is electrically connected to the fourth voltage signal line; the third sub-circuit is configured to be turned on when an abnormal high voltage occurs at the second connection node, so that the second connection point discharges to the third voltage signal line; and the fourth sub-circuit is configured to be turned on when an abnormal low voltage occurs at the second connection node, so that the fourth voltage signal line charges the second connection point.

7. The pixel circuit according to claim 6, wherein the third sub-circuit includes at least one third transistor; the third sub-circuit includes one third transistor; a gate of the third transistor is electrically connected to a second electrode thereof, a first electrode of the third transistor is electrically connected to the second connection point, and the second electrode of the third transistor is electrically connected to the third voltage signal line; or the third sub-circuit includes at least two third transistors connected in series; a gate of each third transistor is electrically connected to a second electrode thereof, a first electrode of a first third transistor in the at least two third transistors is electrically connected to the second connection point, and a second electrode of a last third transistor in the at least two third transistors is electrically connected to the third voltage signal line.

8. The pixel circuit according to claim 6, wherein the fourth sub-circuit includes at least one fourth transistor; the fourth sub-circuit includes one fourth transistor; a gate of the fourth transistor is electrically connected to a second electrode thereof, a first electrode of the fourth transistor is electrically connected to the fourth voltage signal line, and the second electrode of the fourth transistor is electrically connected to the second connection point; or the fourth sub-circuit includes at least two fourth transistors connected in series; a gate of each fourth transistor is electrically connected to a second electrode thereof, a first electrode of a first fourth transistor in the at least two fourth transistors is electrically connected to the fourth voltage signal line, and a second electrode of a last fourth transistor in the at least two fourth transistors is electrically connected to the second connection point.

9. The pixel circuit according to claim 1, wherein the pixel driving circuit includes a first reset transistor, a compensation transistor, a driving transistor, a writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor and a first capacitor; in the first reset transistor, a gate is electrically connected to a reset signal line, a first electrode is electrically connected to a first node, and a second electrode is electrically connected to a first initialization signal line; in the compensation transistor, a gate is electrically connected to a first scan signal line, a first electrode is electrically connected to the first node, and a second electrode is electrically connected to a second node; in the driving transistor, a gate is electrically connected to the first node, a first electrode is electrically connected to a third node, and a second electrode is electrically connected to the second node; in the writing transistor, a gate is electrically connected to the first scan signal line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to a first data signal line; in the first light-emitting control transistor, a gate is electrically connected to a light-emitting control signal line, a first electrode is electrically connected to a first voltage signal line, and a second electrode is electrically connected to the third node; in the second light-emitting control transistor, a gate is electrically connected to the light-emitting control signal line, a first electrode is electrically connected to the second node, and a second electrode is electrically connected to a fourth node; in the second reset transistor, a gate is electrically connected to a second scan signal line, a first electrode is electrically connected to a second initialization signal line, and a second electrode is electrically connected to the fourth node; and in the first capacitor, a first electrode plate is electrically connected to the first voltage signal line, and a second electrode plate is electrically connected to the first node.

10. The pixel circuit according to claim 9, wherein the fourth node of the pixel driving circuit is electrically connected to the first terminal and the third terminal of the bonding unit.

11. An array substrate, comprising a plurality of pixel circuits according to claim 1, wherein the array substrate includes a substrate, a semiconductor layer, a first gate layer, a second gate layer, a first source-drain metal layer, a second source-drain metal layer, and a bonding layer that are stacked; the set voltage signal line is located in one of the first source-drain metal layer or the second source-drain metal layer; the pixel driving circuit is located in the semiconductor layer, the first gate layer, the second gate layer and the first source-drain metal layer; the bonding unit is located in the bonding layer; in a region where at least one pixel circuit is located, the bonding layer includes a first bonding pattern group and at least one second bonding pattern group, the first bonding pattern group includes a first bonding pattern and a second bonding pattern, and a second bonding pattern group includes a third bonding pattern and a fourth bonding pattern; the first bonding pattern group serves as the first bonding terminal group, and the second bonding pattern group serves as the second bonding terminal group; the first bonding pattern and the third bonding pattern are both electrically connected to the pixel driving circuit, and the second bonding pattern and the fourth bonding pattern are both electrically connected to the set voltage signal line.

12. The array substrate according to claim 11, wherein the second source-drain metal layer includes a first source-drain pattern group and at least one second source-drain pattern group; the first source-drain pattern group includes a first source-drain pattern and a second source-drain pattern, and a second source-drain pattern group includes a third source-drain pattern and a fourth source-drain pattern; the first source-drain pattern is electrically connected to the first bonding pattern, and the second source-drain pattern is electrically connected to the second bonding pattern; the third source-drain pattern is electrically connected to the third bonding pattern, and the fourth source-drain pattern is electrically connected to the fourth bonding pattern; the first source-drain pattern and the third source-drain pattern are both electrically connected to the pixel driving circuit, and the second source-drain pattern and the fourth source-drain pattern are both electrically connected to the set voltage signal line.

13. The array substrate according to claim 12, wherein the first source-drain metal layer includes a first connection line, the first connection line is connected to the pixel driving circuit, and the first connection line is further connected to the first source-drain pattern and the third source-drain pattern.

14. The array substrate according to claim 13, wherein the first terminal and the third terminal are connected to a first connection node; the first connection line includes a connection portion located in a middle position of the first connection line, the connection portion serves as the first connection node, and the first source-drain pattern group and the second source-drain pattern group are both non-overlapping with the connection portion.

15. The array substrate according to claim 13, wherein the pixel circuit further includes an electrostatic protection circuit, and the electrostatic protection circuit includes a first transistor and a second transistor; the semiconductor layer includes an active layer of the first transistor and an active layer of the second transistor, and a first end of the active layer of the first transistor and a second end of the active layer of the second transistor are close to and connected to each other; the first source-drain metal layer includes a first connection pattern, a second connection pattern, a third connection pattern and a second connection line; a second end of the active layer of the first transistor is connected to the first connection pattern, and the first connection pattern is further connected to a third voltage signal line; the third voltage signal line overlaps with the active layer of the first transistor; the first end of the active layer of the first transistor is further connected to the second connection pattern, and the second connection pattern is further connected to a gate pattern of the second transistor; the gate pattern of the second transistor overlaps with the active layer of the second transistor; a first end of the active layer of the second transistor is connected to the third connection pattern, and the third connection pattern is further connected to a fourth voltage signal line; and both ends of the second connection line are connected to the first connection line and the second connection pattern.

16. The array substrate according to claim 15, wherein the plurality of pixel circuits are arranged in an array; the first gate layer includes a plurality of third voltage signal lines and a plurality of fourth voltage signal lines extending along a row direction; and each third voltage signal line and each fourth voltage signal line are located in a region where a row of pixel circuits is located.

17. The array substrate according to claim 12, wherein the pixel driving circuit includes a driving transistor; the semiconductor layer includes an active layer of the driving transistor, and the first source-drain pattern group and the second source-drain pattern group are both non-overlapping with the active layer of the driving transistor.

18. The array substrate according to claim 11, wherein the set voltage signal line is located in the first source-drain metal layer, and the set voltage signal line is a first voltage signal line; or the set voltage signal line is located in the second source-drain metal layer, and the set voltage signal line is a second voltage signal line.

19. A display panel, comprising: the array substrate according to claim 11; a plurality of light-emitting devices, wherein each of the plurality of light-emitting devices is electrically connected to the first bonding terminal group or the second bonding terminal group in the array substrate.

20. The display panel according to claim 19, wherein the light-emitting device is one of a micro organic light-emitting diode (micro OLED), a quantum dot light-emitting diode (QLED), a mini light-emitting diode (mini LED) or a micro light-emitting diode (micro LED).