Programmable Fault Violation Filter

1. A device comprising: a digital comparator to receive a digital input value, wherein the digital comparator generates a plurality of outputs comprising at least a first output based on a first programmable threshold value and a second output based on a second programmable threshold value, the first programmable threshold value different from the second programmable threshold value; a first counter coupled to the first output of the plurality of outputs of the digital comparator; a second counter coupled to the second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and a second input coupled to an output of the second counter, the output controller to generate a filtered fault event signal based at least partially on the output of the first counter and the output of the second counter, wherein the output controller asserts a fault event output based at least on a value of the first counter, a first programmable counter limit, a value of the second counter, and a second programmable counter limit and wherein the first and second counters respectively comprise a reset input, and a clock input, and wherein in a first operating mode, a reset input of the first counter is coupled with the second output of the plurality of outputs of the digital comparator wherein the first counter stops counting when the first counter exceeds a first programmable counter limit, and is reset by the second output of the plurality of outputs of the digital comparator, and wherein the second counter is reset when the second counter exceeds a second programmable counter limit.

2. The device as claimed in claim 1, wherein the first programmable threshold value comprises at least one of an upper limit applied to the digital input value and a lower limit applied to the digital input value.

3. The device as claimed in claim 1, wherein the second programmable threshold value comprises at least one of a range of allowed digital input values and a range of restricted digital input values.

4. The device as claimed in claim 1, wherein the first and second counter respectively to count samples of a respective one of the plurality of outputs of the digital comparator.

5. The device as claimed in claim 1, wherein the second counter comprises a decoder to reset the first counter based on the value of the second counter and a programmable condition.

6. The device as claimed in claim 1, wherein in a second operating mode, the first counter stops counting when the first counter exceeds the first programmable counter limit or when the second output of the digital comparator is asserted, and wherein the first and second counter are reset when the second counter exceeds the second programmable counter limit.

7. The device as claimed in claim 1, wherein the device is a programmable peripheral device in a microcontroller.

8. A microcontroller comprising a programmable threshold violation filter, wherein the programmable threshold violation filter comprises: a digital comparator to receive a digital input value, wherein the digital comparator generates a plurality of outputs based on a first programmable threshold value and a second programmable threshold value, the first programmable threshold value different from the second programmable threshold value; a first counter coupled to at least one of the plurality of outputs of the digital comparator; an output controller with a first input coupled to an output of the first counter, the output controller to assert a fault event output when the first counter exceeds a first programmable counter limit and to reset the fault event signal when the first counter exceeds a second programmable counter limit; a second counter coupled to at least one of the plurality of outputs of the digital comparator and an output controller with a second input coupled to an output of the second counter, the output controller to assert a fault event output when the first counter exceeds the first programmable counter limit and to reset the fault event signal when the second counter exceeds the second programmable counter limit, and wherein in a first operating mode, the first counter starts counting when the first output of the plurality of outputs of the digital comparator is asserted, the first counter stops counting when the first counter exceeds the first programmable counter limit, and the first counter is reset by the second output of the plurality of outputs of the digital comparator, and wherein the second counter starts counting when the second output of the plurality of outputs of the digital comparator is asserted and the first counter exceeds the first programmable counter limit, and the second counter is reset when the second counter exceeds the second programmable counter limit.

9. The microcontroller as claimed in claim 8, wherein in a second operating mode, the first counter starts counting when the first output of the digital comparator is asserted, the first counter stops counting when the first counter exceeds the first programmable counter limit or when the second output of the digital comparator is asserted, and the first counter is reset when the second counter exceeds the second programmable counter limit, and wherein the second counter starts counting when the second output of the digital comparator is asserted and the first counter exceeds the first programmable counter limit, and the second counter is reset when the second counter the second programmable counter limit.